EPM5192AQM100-20 vs EPM5192AQI100-15 Comparação
Comparação detalhada lado a lado de EPM5192AQM100-20 por Intel e EPM5192AQI100-15 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 ObsoleteComparação de especificações
| Parâmetro | EPM5192AQM100-20 | EPM5192AQI100-15 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,20 | $21,40 |
| Device Family | MAX 5000 (EPLD / classic CPLD) | — |
| Logic Elements | 192 macrocells across 12 Logic Array Blocks (LABs) | — |
| Number of LABs | 12 | — |
| User I/O Lines | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Pin-to-Pin Propagation Delay (tPD) | 33 ns | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Encapsulamento | 100-pin PQFP (JESD-30 code R-PQFP-G100) | PQFP-100 (R-PQFP-G100), 100-pin Plastic Quad Flat Pack |
| Tipo de montagem | Surface Mount | — |
| Process Technology | CMOS EPROM-based | — |
| Configuration Memory | On-chip EPROM (non-volatile, one-time programmable in this package) | — |
| Boundary-Scan Test | JTAG / IEEE 1149.1 compatible | — |
| External Clock Input | Yes (global clock pin) | — |
| Operating Temperature Grade | [DATA_NEEDED: explicit temperature grade from datasheet] | Industrial (-40C to +85C) - 'I' suffix |
| Tensão de alimentação | [DATA_NEEDED: VCC range from datasheet] | [DATA_NEEDED: VCC typical value] |
| Status RoHS | [DATA_NEEDED: verified from manufacturer product page] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 5000 |
| Series | — | MAX® 5000 EPLD |
| Device Type | — | OT PLD (One-Time-Programmable EPLD), CMOS |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Programmable I/O Lines | — | 64 |
| Total Logical Inputs | — | 72 |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (max datasheet) | — | 25 ns |
| Maximum Internal Frequency | — | 83.3 MHz |
| Programming Method | — | JTAG via Altera programming hardware (ByteBlasterMV, USB-Blaster) |
| Technology | — | CMOS, EPROM-based (UV-erasable on windowed versions, OTP on this part) |