EPM7128AETC144-10 vs EPM7128AETC144-7 Comparação
Comparação detalhada lado a lado de EPM7128AETC144-10 por Altera e EPM7128AETC144-7 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM7128AETC144-10 | EPM7128AETC144-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $21,70 | $16,40 |
| Family | MAX 7000A | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum User I/Os | 36 | — |
| Pin-to-pin Logic Delay (tPD) | 10 ns | — |
| Maximum Internal Counter Frequency | 98 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V | — |
| Temperatura de operação | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Encapsulamento | 144-pin TQFP (also referred to as LQFP-144) | 144-pin TQFP (20x20 mm) |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) |
| Non-volatile Memory | EEPROM, instant-on | — |
| Global Clocks / Global OE | 2 / 2 | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Nível MSL | MSL 3 (per JEDEC J-STD-020) | — |
| Status RoHS | [DATA_NEEDED: rohs status from manufacturer] | [DATA_NEEDED: RoHS status] |
| Series | — | MAX 7000A |
| Programmable Type | — | In-System Programmable (ISP), EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Number of Usable Gates | — | 2,500 |
| Number of I/Os | — | 100 |
| Propagation Delay (tPD) Max | — | 7.5 ns |
| Maximum Operating Frequency | — | 129.9 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V tolerant |
| Configuration Memory | — | EEPROM, non-volatile |
| ISP Endurance | — | 100 cycles typical per macrocell |
| Process Technology | — | CMOS |