EPM7128ATC144-10 vs EPM7128AETC144-7 Comparação
Comparação detalhada lado a lado de EPM7128ATC144-10 por Altera e EPM7128AETC144-7 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM7128ATC144-10 | EPM7128AETC144-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,10 | $16,40 |
| Manufacturer | Altera (now Intel) | — |
| Series | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | In-System Programmable (ISP), EEPROM |
| Macrocells | 128 | — |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 98 MHz | — |
| Supply Voltage - Internal (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Voltage Levels | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) | — |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) | — |
| Temperatura de operação | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Encapsulamento / Caixa | 144-TQFP (20 x 20 mm) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 2nd generation | — |
| Status RoHS | unknown (legacy Altera device) | [DATA_NEEDED: RoHS status] |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Number of Usable Gates | — | 2,500 |
| Number of I/Os | — | 100 |
| Propagation Delay (tPD) Max | — | 7.5 ns |
| Maximum Operating Frequency | — | 129.9 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V tolerant |
| Encapsulamento | — | 144-pin TQFP (20x20 mm) |
| Programming Interface | — | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) |
| Configuration Memory | — | EEPROM, non-volatile |
| ISP Endurance | — | 100 cycles typical per macrocell |
| Process Technology | — | CMOS |