EPM7128SLC84-10 vs EPM7128SLI84-10N Comparação
Comparação detalhada lado a lado de EPM7128SLC84-10 por Intel e EPM7128SLI84-10N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndComparação de especificações
| Parâmetro | EPM7128SLC84-10 | EPM7128SLI84-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,75 | $8,45 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Logic Gates | 2500 | — |
| User I/Os | 68 | 68 |
| Total Package Pins | 84 | — |
| Encapsulamento | PLCC-84 (J-lead) | 84-pin PLCC (J-Lead) |
| Propagation Delay (tpd) | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | — |
| Internal Frequency | 250 MHz | — |
| Supply Voltage (VCCINT) | 5 V | 4.75 V to 5.25 V (5 V typical) |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V | — |
| Program Memory Type | EEPROM (in-system programmable) | — |
| JTAG (IEEE 1149.1) | Yes | — |
| Temperatura de operação | 0C to +70C (Commercial) | -40 C to +85 C (Industrial) |
| Tipo de montagem | Surface Mount (J-bend) | Surface Mount |
| Nível MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | Non-compliant (contains lead in PLCC) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Usable Gates | — | 2,500 |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |