EPM7128SQC100-7N vs EPM7128STC100-6N Comparação
Comparação detalhada lado a lado de EPM7128SQC100-7N por Intel e EPM7128STC100-6N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteAltera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteComparação de especificações
| Parâmetro | EPM7128SQC100-7N | EPM7128STC100-6N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7,10 | $10,50 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Program Memory Type | EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks | 8 | — |
| Number of Global Clocks | 2 | — |
| Product Terms per Macrocell | 32 | — |
| Usable Gates | 2,500 | 2,500 |
| System Gates | 5,000 (max) | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Counter Speed | 175.4 MHz | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Operating Voltage (Core) | 5.0 V | — |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) | — |
| Encapsulamento | 100-pin PQFP (QFP-100) | — |
| Temperatura de operação | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Status RoHS | Compliant (lead-free 'N' suffix) | Non-Compliant (lead-bearing package) |
| Process Technology | 0.30 µm CMOS EEPROM | CMOS EEPROM |
| Security Bit | Programmable (one per device) | — |
| Macro Cells | — | 128 |
| User I/Os | — | 84 |
| Logic Family | — | CMOS |
| Número de pinos | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Propagation Delay (tPD) | — | 6 ns |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Tipo de montagem | — | Surface Mount |