EPM7128STC100-10 vs EPM7128STC100-15N Comparação
Comparação detalhada lado a lado de EPM7128STC100-10 por Altera e EPM7128STC100-15N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoleteIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteComparação de especificações
| Parâmetro | EPM7128STC100-10 | EPM7128STC100-15N |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7,10 | $9,20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| Encapsulamento | TQFP-100 (C100) | 100-pin TQFP |
| Contagem de pinos | 100 | — |
| Tipo de montagem | Surface Mount | — |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | — |
| Temperatura de operação | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Status RoHS | [DATA_NEEDED: RoHS compliance status not in provided data] | Non-RoHS (legacy SnPb finish typical) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | — | 3.3 V or 5 V (per bank) |
| Technology | — | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| Status do ciclo de vida | — | Obsolete (PDN effective 2017-06-01) |