EPM9320LC84-20 vs EPM9320LC84-15 Comparação
Comparação detalhada lado a lado de EPM9320LC84-20 por Altera e EPM9320LC84-15 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM9320LC84-20 | EPM9320LC84-15 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,75 | $17,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Encapsulamento | PLCC-84 (Plastic Leaded Chip Carrier) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | 15 ns (max) |
| Internal Counter Frequency | 118 MHz | — |
| Tensão de alimentação | 5.0 V | — |
| Temperatura de operação | 0 C to 70 C | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Usable Gates | — | 6,000 |
| Logic Array Blocks (LABs) | — | 20 |
| Frequência máxima de clock | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Tipo de montagem | — | Surface Mount |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |