LTC2155CUP-14 vs LTC2150CUJ-14 Comparação
Comparação detalhada lado a lado de LTC2155CUP-14 por Analog Devices e LTC2150CUJ-14 por Analog Devices. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Analog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ AtivoComparação de especificações
| Parâmetro | LTC2155CUP-14 | LTC2150CUJ-14 |
|---|---|---|
| Marca | Analog Devices | Analog Devices |
| Categoria | ADC/DAC | ADC/DAC |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $78,95 | $41,58 |
| Resolução | 14 bit | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 1 |
| Taxa de amostragem | 170 MSPS per channel | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential | — |
| Tipo de saída | Parallel CMOS / DDR LVDS selectable | — |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | 1.7 V to 1.9 V (1.8 V nominal) |
| Analog Input Bandwidth | 1.4 GHz | — |
| SNR | 70.1 dB (at 100 MHz input, per family datasheet) | — |
| SFDR | 88 dB (per family datasheet) | — |
| Power Consumption | [DATA_NEEDED: total power per pair at 170 Msps] | — |
| Encapsulamento | 64-QFN (9x9 mm) with exposed pad | 40-QFN (6 mm × 6 mm) with exposed pad |
| Faixa de temperatura de operação | 0C to +70C (C suffix = commercial) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Nível MSL | [DATA_NEEDED] | — |
| Status RoHS | Compliant (PBF suffix indicates Pb-free) | Compliant (Pb-free #PBF suffix) |
| Sample Rate | — | 170 Msps |
| INL (typical) | — | ±0.85 LSB |
| DNL (typical) | — | ±0.25 LSB |
| Transition Noise | — | 1.82 LSBRMS |
| Missing Codes | — | None over temperature |
| Full-Power Sample/Hold Bandwidth | — | 1.25 GHz |
| Digital Output Interface | — | DDR LVDS |
| Encode Clock Inputs | — | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) |
| Clock Duty-Cycle Stabilizer | — | Optional (selectable) |
| Configuration Interface | — | Serial SPI port |
| Latency | — | 5 clock cycles |
| Power-Saving Modes | — | Sleep and Nap modes |