M1AFS1500-2FG256 vs M1AFS1500-2FG256I Comparação

Comparação detalhada lado a lado de M1AFS1500-2FG256 por Microchip Technology e M1AFS1500-2FG256I por Microchip Technology. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Microchip Technology
M1AFS1500-2FG256 M1AFS1500-2FG256 - Fusion FPGA 1.5M Gates ARM Cortex-M1 | Microchip

M1AFS1500-2FG256 - Fusion FPGA 1.5M Gates ARM Cortex-M1 | Microchip

M1AFS1500-2FG256 ✓ Ativo
Microchip Technology
M1AFS1500-2FG256I M1AFS1500-2FG256I - 1.5M Gate Fusion FPGA with Cortex-M1 | Microchip

M1AFS1500-2FG256I - 1.5M Gate Fusion FPGA with Cortex-M1 | Microchip

M1AFS1500-2FG256I ✓ Ativo

Comparação de especificações

Parâmetro M1AFS1500-2FG256 M1AFS1500-2FG256I
Marca Microchip Technology Microchip Technology
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Ativo Ativo
Status do estoque In Stock In Stock
Preço unitário (USD) $280,68 $152,00
Family Fusion (AFS) Mixed-Signal FPGA, M1 (ARM Cortex-M1) variant Fusion (Mixed-Signal Flash FPGA)
System Gates 1500000 1500000
Logic Cells 38400 38400
User I/O 119 —
Configuration Memory 276480 bits (flash-based) On-chip Flash (non-volatile, secure)
Embedded Processor ARM Cortex-M1 ARM Cortex-M1 (M1 variant)
Core Supply Voltage 1.5 V 1.5 V
Process Technology 130 nm CMOS flash 130 nm Flash-based CMOS
Speed Grade -2 -2
Encapsulamento 256-LBGA (FBGA, 256-ball) 256-ball FBGA (LBGA)
Tipo de montagem Surface Mount Surface Mount
Configuration Non-volatile flash, instant-on, JTAG programming —
Security 128-bit flash lock + AES decryption —
Analog Peripherals Configurable analog blocks (ADC, voltage/current monitors) —
Clock Management Integrated clock generation and management circuitry Integrated clock generation and management circuitry
Temperatura de operação [DATA_NEEDED: Operating Temperature Range] -40C to +100C (Industrial)
Status RoHS Lead free / RoHS Compliant Compliant
Lead Free — Yes
Analog Subsystem — Mixed-signal FPGA with configurable analog blocks and ADC
Packaging — Tray

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