MX574ALEWI+TCDR vs MC145572PBR2 Comparação

Comparação detalhada lado a lado de MX574ALEWI+TCDR por Analog Devices e MC145572PBR2 por NXP Semiconductors. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

NXP Semiconductors
MC145572PBR2 MC145572PBR2 - ISDN U-Interface Transceiver | NXP | 44-LQFP

MC145572PBR2 - ISDN U-Interface Transceiver | NXP | 44-LQFP

MC145572PBR2 Obsolete

Comparação de especificações

Parâmetro MX574ALEWI+TCDR MC145572PBR2
Marca Analog Devices NXP Semiconductors
Categoria ADC/DAC Interface ICs
Status do ciclo de vida Ativo Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $17,10 $5,20
Manufacturer Analog Devices Inc. (formerly Maxim Integrated) NXP Semiconductors (formerly Freescale / Motorola)
MPN MX574ALEWI+TCDR —
Converter Type SAR (Successive Approximation Register) ADC —
Resolução 12 bit —
Number of Inputs 1 —
Input Type Single-Ended (unipolar or bipolar ranges via pin strapping) —
Maximum Conversion Time 25 µs —
Sample Rate (max) 40 kSPS (typ) —
Analog Input Ranges 0 to +5 V, 0 to +10 V, ±5 V, ±10 V (software/strap-selectable) —
Internal Reference +10 V buried Zener, ±0.25 % initial accuracy (typ) —
Data Interface 12-bit parallel, 8-bit parallel, or serial —
Tipo de saída Three-state (high-Z) CMOS-compatible —
Integral Nonlinearity (A grade) ±1 LSB (max) —
Supply Voltages V+ = +12 V or +15 V, V- = -12 V or -15 V, VCC (digital) = +5 V —
Power Consumption 150 mW (typ, ±15 V supply) —
Temperatura de operação 0 °C to +70 °C (commercial, 'L' grade) [DATA_NEEDED: operating temperature range]
Encapsulamento 28-pin SOIC wide-body (SOIC-28W) 44-LQFP (10x10 mm)
Tipo de montagem Surface Mount Surface Mount
Status RoHS Compliant RoHS non-compliant (SnPb finish, per legacy Freescale data)
AEC-Q100 Not qualified (commercial grade) —
Part Type — ISDN U-Interface Transceiver
Tensão de alimentação — 5 V (typical)
Taxa de dados — 160 kbps (2B1Q full-duplex over single twisted pair)
Line Code — 2B1Q (ANSI T1.601-1992)
Interface Standard — ANSI T1.601-1992 / ETSI ETR 080
Operating Modes — NT (Network Termination) and LT (Line Termination), strap-selectable
HDLC Controller — On-chip, up to 4x 16-bit or 2x 32-bit identifiers
Echo Canceller — Integrated adaptive
Scrambler/Descrambler — On-chip
Host Interface — Parallel microprocessor-compatible
Lead-Free Status — Contains lead (legacy PBR2 tape-and-reel part marking)
Series — MC145572
Part Status — Obsolete / Last-time-buy stock only

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