RTAX250SL-CG624E vs RTAX250SL-1CG624E Comparação
Comparação detalhada lado a lado de RTAX250SL-CG624E por Microchip Technology e RTAX250SL-1CG624E por Microchip Technology. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Microchip Technology
RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624E ✓ AtivoMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ AtivoComparação de especificações
| Parâmetro | RTAX250SL-CG624E | RTAX250SL-1CG624E |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $1.375,00 | $1,00 |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| System Gates | 250000 | — |
| Logic Cells (CLBs) | 2816 | — |
| Maximum Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| Supply Voltage Tolerance | +/-0.15 V | — |
| Maximum Combinatorial Delay | 0.93 ns | — |
| Encapsulamento | 624-Pin CCGA (Ceramic Column Grid Array) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Temperatura de operação | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | CMOS |
| Radiation Tolerance | SEU-hardened registers; SEU rate < 10-10 errors/bit-day | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Tipo de montagem | Surface Mount | Surface Mount (ceramic column grid array) |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Programmability | Live at power-up, true single-chip | — |
| Equivalent System Gates | — | 250,000 gates |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| Logic Cells | — | 4224 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |