ATMEGA325PA-AU - 32KB Flash AVR MCU 20MHz TQFP-64 | Microchip
N.º da peça: ATMEGA325PA-AU ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $7.25 | $7,25 |
| 10 | $6.6 | $66,00 |
| 100 | $5.95 | $595,00 |
| 500 | $5.4 | $2.700,00 |
| 1.000 | $4.95 | $4.950,00 |
ATMEGA325PA-AU Visão geral
An 8-bit AVR microcontroller is a Harvard-architecture RISC processor in which Flash program memory, SRAM data memory, and EEPROM are integrated on a single chip alongside peripherals, making it the central control element of an embedded system. Within the power-management IC hierarchy, the ATmega family sits at the MCU level of a broader semiconductor taxonomy: microcontroller -> embedded processor -> integrated circuit. The AVR RISC core executes most of its 131 instructions in a single clock cycle, which is why throughput is measured in MIPS equal to clock frequency.
Key features include 1.8 V to 5.5 V operation across the full speed range, Microchip picoPower technology for nanoamp-class sleep-mode current, an 8-channel 10-bit ADC, and a JTAG interface supporting on-chip debug and boundary scan. Self-programming Flash enables in-application firmware updates and bootloaders without an external programmer beyond initial ICSP.
Technically, the picoPower ATmega325PA improves on the earlier ATmega325P with reduced power consumption in all sleep modes, which matters in battery-powered designs where the MCU spends most of its life in power-down. The AVR core's single-cycle execution and register file of 32 general-purpose working registers keep interrupt latency short and deterministic, valuable in real-time control loops.
Typical applications include industrial sensor nodes and HMI front ends, battery-powered meters and data loggers, and hobbyist or commercial embedded controllers requiring 5 V tolerance and legacy AVR tooling compatibility.
A key design consideration: maximum safe clock frequency depends on supply voltage - at 5 V the part runs to 20 MHz, but at lower VCC the 20 MHz figure may not be guaranteed across the full data-sheet curve, so verify the frequency-versus-voltage graph in the manufacturer datasheet before over-clocking near the low-voltage end.
This page synthesizes distributor pricing, drop-in alternatives within the ATmega325/329/645 family, pinout data, and practical design notes not consolidated in the manufacturer datasheet.
Alternativas drop-in para ATMEGA325PA-AU — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ATMEGA325PA-AU (mesmo formato e footprint) — diferindo em RoHS Status, Instruction Set, Package, Core Architecture, Maximum Clock Frequency.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ATMEGA325PA-AUR
✅ Drop-In✓ Em estoque
$3.9 / unidade
Ver ficha técnica →ATMEGA325P-20AU
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ATMEGA329P-20AUR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ATMEGA169PV-8AUR
✅ Drop-In✓ Em estoque
$4.16 / unidade
Ver ficha técnica →ATMEGA165P-16AU
✅ Drop-In✓ Em estoque
$5.1 / unidade
Ver ficha técnica →ATMEGA645P-20AU
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
ATMEGA325PA-AU Classificações máximas e características elétricas
| Core Architecture | AVR 8-bit RISC |
| Flash Program Memory | 32 KB (16K x 16), self-programming |
| SRAM | 2 KB |
| EEPROM | 1 KB |
| Frequência máxima de clock | 20 MHz |
| Throughput | Up to 20 MIPS at 20 MHz |
| Instruction Set | 131 instructions, most single-cycle |
| Supply Voltage Range | 1.8 V to 5.5 V (picoPower) |
| ADC | 8-channel 10-bit |
| Debug / Programming | JTAG on-chip debug, ICSP |
| Low Power Technology | picoPower |
| Encapsulamento | 64-TQFP, 14 x 14 mm, 0.8 mm pitch |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (green, lead-free per distributor data) |
| Lifecycle Stage | Active |
Configuração de pinos do ATMEGA325PA-AU
| Pino 1 | PF0 (ADC0) — Port F bit 0 / ADC channel 0 input |
| Pino 2 | PF1 (ADC1) — Port F bit 1 / ADC channel 1 input |
| Pino 3 | PF2 (ADC2) — Port F bit 2 / ADC channel 2 input |
| Pino 4 | PF3 (ADC3) — Port F bit 3 / ADC channel 3 input |
| Pino 5 | PF4 (ADC4/TCK) — Port F bit 4 / ADC4 / JTAG test clock |
| Pino 6 | PF5 (ADC5/TMS) — Port F bit 5 / ADC5 / JTAG test mode select |
| Pino 6 | PF6 (ADC6/TDO) — Port F bit 6 / ADC6 / JTAG test data out |
| Pino 7 | PF7 (ADC7/TDI) — Port F bit 7 / ADC7 / JTAG test data in |
| Pino 8 | GND — Ground |
| Pino 9 | VCC — Digital supply voltage |
| Pino 10 | GND — Ground |
| Pino 11 | AVCC — Analog supply for ADC |
| Pino 12 | PA0 (AD0) — Port A bit 0 (external memory bus / GPIO) |
| Pino 13 | PA1 (AD1) — Port A bit 1 |
| Pino 14 | PA2 (AD2) — Port A bit 2 |
| Pino 15 | PA3 (AD3) — Port A bit 3 |
| Pino 16 | PA4 (AD4) — Port A bit 4 |
| Pino 17 | PA5 (AD5) — Port A bit 5 |
| Pino 18 | PA6 (AD6) — Port A bit 6 |
| Pino 19 | PA7 (AD7) — Port A bit 7 |
| Pino 20 | PB0 (SS) — Port B bit 0 / SPI slave select |
| Pino 21 | PB1 (SCK) — Port B bit 1 / SPI clock |
| Pino 22 | PB2 (MOSI) — Port B bit 2 / SPI master out |
| Pino 23 | PB3 (MISO) — Port B bit 3 / SPI master in |
| Pino 24 | PB4 (OC0) — Port B bit 4 / Timer0 output compare |
| Pino 25 | PB5 (OC1A) — Port B bit 5 / Timer1 output compare A |
| Pino 26 | PB6 (OC1B) — Port B bit 6 / Timer1 output compare B |
| Pino 27 | PB7 (OC2) — Port B bit 7 / Timer2 output compare |
| Pino 28 | RESET — Active-low reset input |
| Pino 29 | PC0 (A8) — Port C bit 0 |
| Pino 30 | PC1 (A9) — Port C bit 1 |
| Pino 31 | PC2 (A10) — Port C bit 2 |
| Pino 32 | PC3 (A11) — Port C bit 3 |
| Pino 33 | PC4 (A12) — Port C bit 4 |
| Pino 34 | PC5 (A13) — Port C bit 5 |
| Pino 35 | PC6 (A14) — Port C bit 6 |
| Pino 36 | PC7 (A15) — Port C bit 7 |
| Pino 37 | PD0 (RXD) — Port D bit 0 / USART receive |
| Pino 38 | PD1 (TXD) — Port D bit 1 / USART transmit |
| Pino 39 | PD2 (INT0) — Port D bit 2 / external interrupt 0 |
| Pino 40 | PD3 (INT1) — Port D bit 3 / external interrupt 1 |
| Pino 41 | PD4 (XCK) — Port D bit 4 / USART external clock |
| Pino 42 | PD5 (OC0A) — Port D bit 5 / Timer0 output compare A |
| Pino 43 | PD6 (ICP1) — Port D bit 6 / Timer1 input capture |
| Pino 44 | PD7 (OC1A) — Port D bit 7 / Timer1 output compare A |
| Pino 45 | PE0 (ICP3) — Port E bit 0 / Timer3 input capture |
| Pino 46 | PE1 (OC3A) — Port E bit 1 / Timer3 output compare A |
| Pino 47 | PE2 (OC3B) — Port E bit 2 / Timer3 output compare B |
| Pino 48 | PE3 (TOSC2) — Port E bit 3 / Timer oscillator output 2 |
| Pino 49 | PE4 (TOSC1) — Port E bit 4 / Timer oscillator input 1 |
| Pino 50 | PG0 (WR) — Port G bit 0 / external memory write strobe |
| Pino 51 | PG1 (RD) — Port G bit 1 / external memory read strobe |
| Pino 52 | PG2 (ALE) — Port G bit 2 / address latch enable |
| Pino 53 | XTAL2 — Crystal oscillator output |
| Pino 54 | XTAL1 — Crystal oscillator input / external clock |
| Pino 55 | PH0 (SCL/INT0) — Port H bit 0 / TWI clock / external interrupt |
| Pino 56 | PH1 (SDA/INT1) — Port H bit 1 / TWI data / external interrupt |
| Pino 57 | PH2 (RXD1) — Port H bit 2 |
| Pino 58 | PH3 (TXD1) — Port H bit 3 |
| Pino 59 | PH4 (OC4A) — Port H bit 4 |
| Pino 60 | PH5 (OC4B) — Port H bit 5 |
| Pino 61 | PH6 (OC4C) — Port H bit 6 |
| Pino 62 | PH7 (OC2A) — Port H bit 7 |
| Pino 63 | PJ0 (PCINT0) — Port J bit 0 / pin change interrupt 0 |
| Pino 64 | PJ1 (PCINT1) — Port J bit 1 / pin change interrupt 1 |
Aplicações típicas
ATMEGA325PA-AU é adequado para 6 aplicaçãos: Battery-Powered Metering and Data Logging, Industrial Sensor Nodes and HMI Front Ends, Legacy 5V Embedded Controllers, Analog Signal Acquisition Systems, Consumer and Hobbyist Embedded Projects, Firmware-Updatable Field Devices.
Battery-Powered Metering and Data Logging
The ATMEGA325PA-AU is well suited to battery-powered meters and loggers because its picoPower technology minimizes current draw in all sleep modes and its 1.8 V to 5.5 V supply range allows direct operation from three alkaline cells or a single lithium cell via a simple regulator. The 1 KB EEPROM stores calibration constants and logged readings across power cycles without wearing the 32 KB Flash program memory. In a typical topology the device sleeps in power-down between samples, wakes on a timer or external interrupt, performs an 8-channel 10-bit ADC conversion, timestamps data, and returns to sleep - the PA revision's reduced sleep current directly extends field battery life versus the non-PA ATmega325P.
Recomendado
Industrial Sensor Nodes and HMI Front Ends
In industrial environments the ATMEGA325PA-AU provides 5 V-tolerant I/O, JTAG on-chip debugging for production diagnostics, and a deterministic 8-bit AVR core with 131 mostly single-cycle instructions - ideal for polling sensors, debouncing keys, and driving segment displays in HMI front ends. The 32 KB self-programming Flash supports field firmware updates through a bootloader, reducing service visits. Placed between an RS-485 or sensor front end and actuator drivers, the MCU handles the real-time loop while the JTAG port enables boundary-scan test of the assembled board, a quantified manufacturing benefit that pure-ICSP-only parts do not offer.
Recomendado
Legacy 5V Embedded Controllers
Many installed industrial designs still run 5 V logic, and the ATMEGA325PA-AU remains fully specified at 5 V with up to 20 MHz operation, making it a natural maintenance part for legacy AVR-based controllers. Because the AVR core and peripheral set are stable across the ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A datasheet family, firmware written years ago for an ATmega325 or 325P typically recompiles without change on the PA. This longevity and source compatibility reduce the engineering cost of servicing long-lifecycle equipment compared with migrating to a modern MCU family.
Recomendado
Analog Signal Acquisition Systems
The integrated 8-channel 10-bit ADC of the ATMEGA325PA-AU lets a single chip acquire up to eight analog inputs without an external converter, lowering BOM cost in multi-sensor acquisition nodes. Channels can be muxed to internal references, and the AVR core processes readings locally, sending only results over a serial link. For noise-sensitive measurements, the picoPower sleep modes allow sampling between power-down intervals that reduce self-heating drift. Note that 10-bit resolution limits precision applications - for sub-LSB accuracy add external conditioning or an external delta-sigma ADC, but for threshold detection and coarse telemetry the on-chip ADC is typically sufficient.
Recomendado
Consumer and Hobbyist Embedded Projects
The ATmega family remains a default choice for hobby and maker platforms because AVR toolchains, bootloaders, and community code are exceptionally mature. The ATMEGA325PA-AU offers 54-class I/O on the 64-TQFP footprint and JTAG debugging accessible with low-cost tools such as the MPLAB SNAP, which Microchip documents as connecting via an 8-pin SIL header using two I/O pins plus reset. The 20 MIPS throughput comfortably handles motor PWM, display refresh, and simple protocol stacks. For hobby boards the TQFP-64 footprint is hand-solderable with drag-soldering, unlike fine-pitch BGA alternatives.
Recomendado
Firmware-Updatable Field Devices
The 32 KB self-programming Flash of the ATMEGA325PA-AU enables bootloader-based firmware updates in deployed equipment: a small resident bootloader rewrites the application section over UART, SPI, or I2C without a programmer on site. Combined with the 1 KB EEPROM for storing version metadata and rollback flags, this supports robust A/B-style update schemes in devices such as access-control panels and HVAC controllers. JTAG additionally allows brick-level recovery in manufacturing RMA. Design the PCB so bootload pins are accessible on a connector to exploit this capability fully in the field.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ATMEGA325PA-AU — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ATMEGA325PA-AUR | ATMEGA325P-20AU | ATMEGA329P-20AUR | ATMEGA165P-16AU |
|---|---|---|---|---|---|
| Package | 64-TQFP (14 x 14 mm) | 64-TQFP - same | 64-TQFP - same | 64-TQFP - same | 64-TQFP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 32 KB | 32 KB | 32 KB | 32 KB | 16 KB |
| SRAM | 2 KB | 2 KB | 2 KB | 2 KB | 1 KB |
| Max Clock Frequency | 20 MHz | 20 MHz | 20 MHz | 20 MHz | 16 MHz |
| Supply Voltage | 1.8 V to 5.5 V (picoPower) | 1.8 V to 5.5 V (picoPower) | 4.5 V to 5.5 V for 20 MHz (P-class) | 4.5 V to 5.5 V for 20 MHz | 2.7 V to 5.5 V for 16 MHz |
| LCD Controller | No | No | No | Yes (segment LCD) | No |
| Sleep-Mode Power Class | picoPower (lowest) | picoPower (lowest) | P-class (higher sleep current) | P-class | P-class |
| Debug Interface | JTAG + ICSP | JTAG + ICSP | JTAG + ICSP | JTAG + ICSP | JTAG + ICSP |
Principais diferenciais
- picoPower sleep-mode optimization (vs ATMEGA325P-20AU)
- No LCD pin overhead for maximum general-purpose I/O (vs ATMEGA329P-20AUR)
- 20 MHz performance in 1.8-5.5V envelope (vs ATMEGA165P-16AU)
- Cost vs memory trade-off possible without redesign (vs ATMEGA645P-20AU)
Notas de projeto
Match the clock frequency to the supply voltage. The 20 MHz rating applies at the upper end of the 1.8 V to 5.5 V range; running 20 MHz at low VCC violates the frequency-voltage derating curve. For battery designs, run the MCU at 1.8-3.6 V with a proportionally lower clock, or use the internal RC oscillator and dynamic clock switching. Estimated: halving clock frequency approximately halves active-mode dynamic current, so a 1 MHz internal clock at 3 V drastically extends battery life versus 20 MHz at 5 V in duty-cycled applications.
Decouple every VCC and AVCC pin with 100 nF ceramic capacitors placed within 5 mm of each pin, and tie AVCC to VCC through a low-pass filter (e.g., 10 ohm series resistor plus 100 nF) when ADC accuracy matters. Keep analog traces away from the XTAL pins and JTAG lines. The 64-TQFP exposed pattern in the datasheet uses 0.8 mm pitch - verify the land pattern against the latest Microchip PCB footprint library rather than copying from older Atmel-era layout files.
The JTAG interface is enabled by default from the factory and shares pins PF4-PF7 with ADC channels 4-7. If your application uses those ADC channels, disable JTAG via the JTD bit or fuse settings early in firmware, otherwise the ADC readings on PF4-PF7 will be corrupted. Additionally, confirm reset polarity and the reset pin fuse configuration before production - disabling the external reset fuse makes ICSP reprogramming impossible in the field.
Pinout differences within the family: ATMEGA329 variants dedicate many pins to the segment LCD and differ in port mapping, and the ATmega3250 is a 100-pin part. Do not assume a TQFP-64 footprint swap is safe across the ATmega datasheet family without comparing pin tables pin by pin; the alternatives on this page are footprint-compatible but not always firmware-identical. Test the substitute on one board before committing a production change.
Informações de conformidade
Distributor listings (TrustCompo, Mouser Ind Grn designation) identify the part as RoHS-compliant, lead-free, green. REACH, halogen-free, and conflict-minerals declarations were not found in the retrieved data.
