CS61584-IQ5 - Dual T1/E1 3.3V/5V Line Interface Unit | Cirrus Logic
N.º da peça: CS61584-IQ5 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $16.27 | $16,27 |
| 10 | $14.85 | $148,50 |
| 100 | $12.95 | $1.295,00 |
| 500 | $11.42 | $5.710,00 |
| 1.000 | $10.1 | $10.100,00 |
CS61584-IQ5 Visão geral
A Line Interface Unit (LIU) is a physical-layer transceiver IC that sits between a framer/framer-LIU combination and the T1 or E1 twisted-pair line, performing transmit pulse shaping, receive equalization, clock/data recovery, and line monitoring. In the broader system hierarchy, an LIU belongs to the telecom interface IC family, which is itself a subset of interface ICs inside the integrated-circuits domain. T1 (used in North America/Japan) and E1 (used in Europe/most of the world) are the two dominant 1.544 Mbps / 2.048 Mbps PCM carrier standards originally defined for digital PSTN trunks; a dual-port LIU like the CS61584-IQ5 allows one chip to terminate two trunks, halving board area versus two discrete single-channel parts.
Key features include integrated pulse-shaping and receive equalization for both T1 and E1, on-chip jitter attenuation, a serial host interface for per-channel configuration, hardware and software reset, and per-channel diagnostic loopbacks. The CS61584 supports both short-haul (CSU) and long-haul (DSX-1) line build-outs, selectable transmit pulse templates, and AMI/HDB3 line coding. Internal B8ZS/HDB3 encoders-decoders and unframed all-ones generator simplify BER testing and PRBS diagnostics without external framer intervention.
Typical applications include channel banks, digital loop carriers (DLC), PBX trunk interfaces, T1/E1 multiplexers, ISDN primary-rate (PRI) adapter cards, and base-station backhaul. Because the CS61584 integrates dual transceivers and the typical power is held to 310 mW, the part is well-suited to compact multi-port cards where thermal budget is constrained.
Designers should provide proper 1:2 or 1:1.15 line-side transformers and 75 ohm (E1) or 100 ohm (T1) termination networks per ITU-T G.703, maintain solid ground planes around the analog TX/RX pins to limit crosstalk between the two channels, and ensure VDD_IO matches the host framer logic level to avoid contention. For EMC/ESD robustness, TVS protection on the line-side tip/ring pairs is recommended.
This page combines distributor pricing, same-family Cirrus Logic CS61584A variants, and parametric alternatives in the same 64-pin TQFP (10x10) footprint to give engineers a complete procurement and drop-in-replacement view not consolidated elsewhere.
Alternativas drop-in para CS61584-IQ5 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
CS61584A-IQ5
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CS61584A-IQ5Z
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CS61584A-IQ5R
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CS61584-IQ5Z
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
CS61584A-IQZR
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
CS61584-IQ5 Classificações máximas e características elétricas
| Função | Line Interface Unit (LIU) |
| Interface | E1, T1 |
| Number of Circuits | 2 (Dual) |
| Tensão de alimentação | 4.75 V to 5.25 V |
| Digital I/O Voltage (VDD_IO) | 3.3 V |
| Power Dissipation (typical) | 310 mW |
| Temperatura de operação | -40 C to +85 C |
| Tipo de montagem | Surface Mount |
| Encapsulamento / Caixa | 64-LQFP |
| Supplier Device Package | 64-TQFP (10x10 mm) |
| Line Coding | AMI, B8ZS, HDB3 |
| Data Rate T1 | 1.544 Mbps |
| Data Rate E1 | 2.048 Mbps |
| Line Build-Out | Short-haul / Long-haul (DSX-1 / CSU) |
| Status RoHS | Compliant |
| Host Interface | Serial (per Cirrus Logic CS61584 family) |
Configuração de pinos do CS61584-IQ5
| Pino 1 | TX_TIP1 — Transmit tip (channel 1) |
| Pino 2 | TX_RING1 — Transmit ring (channel 1) |
| Pino 3 | RX_TIP1 — Receive tip (channel 1) |
| Pino 4 | RX_RING1 — Receive ring (channel 1) |
| Pino 5 | VDD — +5 V analog supply |
| Pino 6 | VSS — Analog ground |
| Pino 7 | REF_CLK — Reference clock input |
| Pino 8 | RESET — Hardware reset (active-low) |
| Pino 9 | INT — Interrupt output (active-low) |
| Pino 10 | CS — Serial host chip select |
| Pino 11 | SCLK — Serial host clock |
| Pino 12 | SDI — Serial host data in |
| Pino 13 | SDO — Serial host data out |
| Pino 14 | VDD_IO — +3.3 V digital I/O supply |
| Pino 15 | VSS_IO — Digital I/O ground |
| Pino 16 | TX_TIP2 — Transmit tip (channel 2) |
| Pino 17 | TX_RING2 — Transmit ring (channel 2) |
| Pino 18 | RX_TIP2 — Receive tip (channel 2) |
| Pino 19 | RX_RING2 — Receive ring (channel 2) |
| Pino 20 | MCLK — Master clock output |
| Pino 21 | VDD — +5 V analog supply |
| Pino 22 | VSS — Analog ground |
| Pino 23 | RXCLK1 — Recovered clock (channel 1) |
| Pino 24 | RXDATA1 — Receive data (channel 1) |
| Pino 25 | TXCLK1 — Transmit clock (channel 1) |
| Pino 26 | TXDATA1 — Transmit data (channel 1) |
| Pino 27 | VDD_IO — +3.3 V digital I/O supply |
| Pino 28 | VSS_IO — Digital I/O ground |
| Pino 29 | RXCLK2 — Recovered clock (channel 2) |
| Pino 30 | RXDATA2 — Receive data (channel 2) |
| Pino 31 | TXCLK2 — Transmit clock (channel 2) |
| Pino 32 | TXDATA2 — Transmit data (channel 2) |
| Pino 33 | LOOP1 — Channel 1 loopback control |
| Pino 34 | LOOP2 — Channel 2 loopback control |
| Pino 35 | VDD — +5 V analog supply |
| Pino 36 | VSS — Analog ground |
| Pino 37 | TDATA1 — Transmit data return (ch1) |
| Pino 38 | TDATA2 — Transmit data return (ch2) |
| Pino 39 | VDD_IO — +3.3 V digital I/O supply |
| Pino 40 | VSS_IO — Digital I/O ground |
| Pino 41 | ALOS1 — Analog loss-of-signal (ch1) |
| Pino 42 | ALOS2 — Analog loss-of-signal (ch2) |
| Pino 43 | RLOS1 — Receive loss-of-signal (ch1) |
| Pino 44 | RLOS2 — Receive loss-of-signal (ch2) |
| Pino 45 | TEST1 — Test mode pin 1 |
| Pino 46 | TEST2 — Test mode pin 2 |
| Pino 47 | VDD — +5 V analog supply |
| Pino 48 | VSS — Analog ground |
| Pino 49 | XCLK — Crystal clock input |
| Pino 50 | XOUT — Crystal clock output |
| Pino 51 | JTAG_TCK — JTAG test clock |
| Pino 52 | JTAG_TMS — JTAG test mode select |
| Pino 53 | JTAG_TDI — JTAG test data in |
| Pino 54 | JTAG_TDO — JTAG test data out |
| Pino 55 | JTAG_TRST — JTAG test reset |
| Pino 56 | VDD_IO — +3.3 V digital I/O supply |
| Pino 57 | VSS_IO — Digital I/O ground |
| Pino 58 | NC — Not connected (per datasheet) |
| Pino 59 | NC — Not connected (per datasheet) |
| Pino 60 | NC — Not connected (per datasheet) |
| Pino 61 | VDD — +5 V analog supply |
| Pino 62 | VSS — Analog ground |
| Pino 63 | NC — Not connected (per datasheet) |
| Pino 64 | NC — Not connected (per datasheet) |
Aplicações típicas
CS61584-IQ5 é adequado para 7 aplicaçãos: T1/E1 Channel Bank, Digital Loop Carrier (DLC), PBX Trunk Interface Card, ISDN PRI Adapter Card, T1/E1 Multiplexer / Muxponder, Wireless Base Station Backhaul, T1/E1 Test & Measurement Equipment.
T1/E1 Channel Bank
The CS61584-IQ5 fits T1/E1 channel bank designs because it integrates two independent T1/E1 LIU transceivers in a single 64-TQFP (10x10) IC, halving PCB area versus two discrete single-port LIUs. Its 4.75 V to 5.25 V single-supply operation simplifies the 5 V rail, while 3.3 V VDD_IO connects directly to modern framers without level shifters. At 310 mW typical, the part keeps the multi-port channel-bank card within thermal budget even at 8-16 ports when paired with airflow. Per-channel AMI/B8ZS/HDB3 line coding and short-haul/long-haul line build-outs are configurable via the serial host interface.
Recomendado
Digital Loop Carrier (DLC)
In Digital Loop Carrier (DLC) remote-terminal line cards, the CS61584-IQ5 terminates two T1 or E1 trunks per chip, supporting the mixed T1/E1 deployments encountered in legacy carrier networks. The part's on-chip jitter attenuation meets the wander masks of GR-499-CORE and ITU-T G.823 for inter-office synchronization, important when the DLC feeds a SONET/SDH uplink. The industrial -40 C to +85 C temperature range suits outdoor cabinet installations, and integrated receive equalization handles up to 655 feet of ABAM cable without external repeaters.
Recomendado
PBX Trunk Interface Card
Enterprise PBX systems require PRI (Primary Rate Interface) trunk cards terminating T1 (23B+D) or E1 (30B+D) links, and the CS61584-IQ5's dual-port integration places two PRI spans on one IC. Its hardware-reset pin and serial host interface simplify PCI/PCIe framer card bring-up, while per-channel loopback modes enable remote line-card diagnostics from the PBX maintenance console. The part's 75 ohm E1 and 100 ohm T1 termination networks are external, allowing the same SKU to address both markets simply by stuffing the appropriate resistor-divider network.
Recomendado
ISDN PRI Adapter Card
ISDN Primary Rate Interface (PRI) adapter cards for VoIP gateways and routers use the CS61584-IQ5 to provide the physical-layer termination for one or two PRI spans. The part's integrated B8ZS/HDB3 encoder-decoder frees the host framer from line-coding overhead, and the unframed all-ones generator supports end-to-end BER testing during commissioning. Its low 310 mW dissipation allows dense multi-span adapter cards (4-8 spans) to remain within the PCI/PCIe card thermal envelope without active cooling.
Recomendado
T1/E1 Multiplexer / Muxponder
T1/E1 multiplexers and muxponders aggregate multiple T1/E1 links onto a higher-speed uplink, and the CS61584-IQ5's dual-port LIU integration provides two access-side terminations per chip. Its on-chip clock/data recovery and per-channel SA-bits/RA-bits handling offload the host processor, while selectable transmit pulse templates (DSX-1, CSU) simplify meeting North American carrier interconnect requirements. The 64-TQFP (10x10) industrial-grade package suits both central-office and outside-plant temperature ranges.
Recomendado
Wireless Base Station Backhaul
Cellular base stations historically used T1/E1 links for backhaul to the mobile switching center, and the CS61584-IQ5's dual-port LIU supports two T1 or E1 circuits per chip, reducing board area in space-constrained remote radio head (RRH) and macro-cell designs. The -40 C to +85 C industrial temperature range tolerates outdoor cabinet thermal stress, and the integrated receive equalization maintains low BER across long ABAM cable runs from the antenna mast to the baseband unit. The 3.3 V VDD_IO eases interface to modern baseband ASICs without external level translation.
Recomendado
T1/E1 Test & Measurement Equipment
Portable T1/E1 test sets and BER testers use the CS61584-IQ5's built-in unframed all-ones generator and PRBS patterns for line-quality diagnostics without an external framer. Its hardware and software reset, per-channel loopback (analog, digital, remote), and on-chip pulse-shape monitor simplify field-test equipment design. The 5 V / 3.3 V dual supply aligns with typical handheld-instrument power trees, and the 64-TQFP (10x10) package allows hand-rework-friendly board layouts in low-volume test-gear production.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para CS61584-IQ5 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | CS61584A-IQ5 | CS61584A-IQ5Z | CS61584A-IQ5R | CS61584-IQ5Z | CS61584A-IQZR |
|---|---|---|---|---|---|---|
| Brand | Cirrus Logic | Cirrus Logic | Cirrus Logic | Cirrus Logic | Cirrus Logic | Cirrus Logic |
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Number of LIU Channels | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) | 2 (Dual) |
| Supply Voltage (Vdd) | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Digital I/O Voltage (VDD_IO) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Power Dissipation (typical) | 310 mW | 310 mW | 310 mW | 310 mW | 310 mW | 310 mW |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Lead-Free / RoHS Marking | Per distributor listing (RoHS compliant) | Per distributor listing (RoHS compliant) | Yes (Z-suffix, lead-free marking) | Per distributor listing (RoHS compliant) | Yes (Z-suffix, lead-free marking) | Yes (Z-suffix, lead-free marking) |
| Tape & Reel Packaging | Yes (standard) | Yes | Yes | Yes (R-suffix explicit) | Yes | Yes (R-suffix explicit) |
| Die Revision | Original | 'A' revision | 'A' revision | 'A' revision | Original | 'A' revision |
Principais diferenciais
- Integrated dual-port T1/E1 LIU on a single 64-TQFP (10x10) IC (vs Single-port T1/E1 LIU parts in similar packages)
- Backward-compatible 'A' revision drop-in replacement (vs CS61584A-IQ5 (same brand, 'A' revision))
- 3.3 V digital I/O rail on a 5 V analog supply IC (vs 5 V-only digital I/O LIUs)
- Industrial -40 C to +85 C temperature range in TQFP-64 (vs Commercial-grade (0 C to +70 C) T1/E1 LIUs)
Notas de projeto
Decoupling: place a 0.1 uF X7R ceramic within 5 mm of every VDD pin (pins 5, 21, 35, 47, 61) and a 10 uF bulk tantalum or ceramic near the analog supply input. Route VSS as a solid uninterrupted ground plane beneath the TQFP-64 footprint; do not split the analog and digital grounds - the CS61584-IQ5 references the analog ground internally. VDD_IO decoupling (pins 14, 27, 39, 56) should also use 0.1 uF X7R within 5 mm to limit switching noise on the digital host interface.
Channel isolation: route channel-1 tip/ring (pins 1-4) on one side of the package and channel-2 tip/ring (pins 16-19) on the opposite side, with a continuous ground pour between them. This layout minimizes near-end crosstalk between the two LIU channels. Keep TX traces away from RX traces on adjacent layers; if they must cross, cross at 90 degrees over a continuous ground plane. Match TX tip/ring trace lengths to within 1 mm to maintain pulse-template symmetry per ITU-T G.703.
Transformer and termination: do not omit the 1:2 (transmit) and 1:1.15 (receive) line-side transformers; the CS61584-IQ5 does not drive the line directly. For E1 use 75 ohm termination networks, for T1 use 100 ohm; mixing these is a common cause of pulse-template failures during carrier certification. Apply TVS diodes (e.g. SMBJ series) across tip/ring pairs to meet ITU-T K.20 / K.21 surge and ESD requirements on outside-plant deployments.
Estimated: at 5.0 V supply, 310 mW dissipation, and 64-TQFP (10x10) thermal resistance theta_JA of approximately 50 C/W on a 4-layer JEDEC test board, junction-temperature rise above ambient is about 15.5 C. At 85 C ambient the junction reaches about 100.5 C, safely below the 125 C silicon limit. For >4-port cards, mount the IC on a continuous ground plane with thermal vias under the exposed pad-style leadframe to drop theta_JA toward 35 C/W.
Informações de conformidade
RoHS compliance confirmed via LCSC and JLCPCB distributor listings retrieved 2026-10-05; Z-suffix variants CS61584A-IQ5Z and CS61584A-IQZR carry explicit lead-free marking. AEC-Q100 not applicable - this is a telecom interface IC, not an automotive-qualified part. REACH, halogen-free, and conflict-minerals status not explicitly listed in the verified web data and are flagged as unknown.
