DS90CF388VJD - 3.3V Dual-Pixel LVDS Receiver | TI
N.º da peça: DS90CF388VJD ✓ AtivoDS90CF388VJD Visão geral
A dual-pixel LVDS display interface is a high-speed serial link used to reduce the number of conductors required between a video source and a flat-panel display. LVDS, or Low Voltage Differential Signalling, transfers complementary data signals across differential pairs. The dual-pixel arrangement processes two 24-bit pixel streams in parallel, allowing 48 bits of color information to be carried over eight LVDS data lanes. The DS90CF388VJD is therefore positioned within the broader hierarchy of display-interface ICs, interface ICs, and semiconductors.
The principal features include compliance with the OpenLDI specification for digital display interfaces and support for panel resolutions from SVGA through QXGA. The interface provides DC-balanced data transmission, which helps maintain suitable duty-cycle characteristics across the serial links. At the receiver, cable deskew corrects pair-to-pair skew of plus or minus one LVDS data-bit time, supporting clock rates up to 80 MHz. Control information including VSYNC, HSYNC, DE, and two user-defined signals is transmitted during blanking intervals.
The DS90CF388 is intended to be used with the DS90C387 transmitter as an endpoint pair for dual-pixel CMOS/TTL display links. Differential signaling reduces sensitivity to common-mode noise compared with single-ended parallel routing, while balanced data transfer helps limit electromagnetic interference. Receiver-side deskew compensates for propagation-delay differences between the eight LVDS data channels and therefore supports longer or less uniformly routed cable connections when the implementation follows the manufacturer’s layout and termination requirements.
Typical applications include QXGA flat-panel monitor interfaces, industrial display controllers, digital signage systems, point-of-sale terminals, and embedded human-machine-interface panels. In a typical link, the host supplies parallel CMOS/TTL pixel and control data to the DS90C387, which serializes the information across LVDS pairs. The DS90CF388 receives those pairs, performs deskew and data recovery, and presents the reconstructed pixel information to the downstream display electronics.
PCB implementation should preserve the differential signal topology recommended by the manufacturer, including controlled impedance, symmetrical routing, and suitable LVDS termination. Input and output interface traces should be evaluated for connector and cable parasitics, while the TQFP layout must provide adequate fanout around all 100 leads. The receiver should be placed according to the signal path so that the 80 MHz maximum clock-rate capability is not undermined by unequal routing or excessive external loading.
This product page combines the functional description, package details, pin-compatible ordering variants, interface applications, and design considerations needed to evaluate the DS90CF388VJD. It also distinguishes exact drop-in ordering options from functionally similar devices that may require different circuit implementation, helping engineers confirm PCB compatibility before approving a replacement.
Alternativas drop-in para DS90CF388VJD — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
DS90CF388VJDX
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90CF388VJD/NOPB
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90CF388VJD Especificações
| Product Type | Dual-pixel LVDS display-interface receiver |
| Tensão de alimentação | 3.3 V |
| Supported Panel Resolutions | SVGA through QXGA |
| Maximum Clock Rate | 80 MHz |
| Receiver Deskew | plus or minus 1 LVDS data-bit time |
| Transmitter Input Data Width | 48 bits, dual-pixel 24-bit color |
| LVDS Data Lane Count | 8 streams |
| Logic Input Signal Type | CMOS/TTL |
| Output Signal Type | LVDS differential signaling |
| Control Signals Carried During Blanking | VSYNC, HSYNC, DE, and 2 user-defined signals |
| Display Interface Standard | OpenLDI |
| Data Transmission Balance | DC-balanced |
| Package Type | 100-pin TQFP |
| Package Dimensions | 14 mm x 14 mm |
| Tipo de montagem | Surface mount |
| Interface Direction | Receiver |
| Paired Transmitter | DS90C387 |
Guia de Configuração de Pinos do DS90CF388VJD 14 mm x 14 mm
Configuração de pinos para DS90CF388VJD (pacote 14 mm x 14 mm). A numeração dos pinos, funções e diagramas de conexão estão definidos no datasheet do fabricante. Consulte-o para o footprint exato e diretrizes de soldagem.
Nenhum dado detalhado de pinagem disponível para DS90CF388VJD.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
DS90CF388VJD é adequado para 6 aplicaçãos: QXGA Flat-Panel Monitor Interface, Industrial Display Controller, Digital Signage Display, Point-of-Sale Terminal Display, Embedded Human-Machine Interface, Video Processing Module.
QXGA Flat-Panel Monitor Interface
The DS90CF388VJD fits the receiving side of a QXGA flat-panel link when paired with the DS90C387 transmitter. Its eight LVDS streams carry dual-pixel 24-bit color information derived from 48 bits of CMOS/TTL data, while VSYNC, HSYNC, DE, and two user-defined signals are carried during blanking. Receiver deskew of plus or minus one LVDS data-bit time addresses unequal arrival time among the eight channels. The implementation should use the manufacturer’s recommended controlled-impedance routing and termination so that channel skew and connector parasitics remain compatible with the stated 80 MHz maximum clock rate.
Recomendado
Industrial Display Controller
The DS90CF388VJD is suitable for an industrial display controller that connects a host processor to a high-resolution flat panel over a serialized link. Its 3.3 V operation, eight LVDS data streams, and support for SVGA-through-QXGA panels reduce parallel routing across a larger enclosure. The DS90C387 accepts 48 bits of CMOS/TTL dual-pixel data and serializes it for the receiver. Industrial designs should preserve differential-pair geometry, account for cable length and connector effects, and validate timing and EMC performance over the complete operating-temperature and enclosure environment.
Recomendado
Digital Signage Display
The DS90CF388VJD can serve as the panel-side receiver in a digital-signage system that transports high-resolution video and control data from a distant controller. Serialized LVDS reduces the number of signal conductors compared with a parallel interface, and the receiver’s deskew function compensates pair-to-pair delay of up to plus or minus one data-bit time. Blanking-period transfer of VSYNC, HSYNC, DE, and two user-defined signals supports synchronization between the host and panel electronics. Cable selection, connector grounding, and controlled-impedance PCB routing remain critical to reliable operation across the full supported clock-rate range.
Recomendado
Point-of-Sale Terminal Display
The DS90CF388VJD supports the display link in a point-of-sale terminal that drives a compact flat panel from a host or embedded controller. The dual-pixel architecture carries two 24-bit color streams over eight LVDS data lanes and supports resolutions up to QXGA, making it suitable for detailed transaction interfaces, menus, and product images. The 100-pin TQFP receiver requires careful escape routing from the connector or cable interface to the device. Layout should follow the manufacturer’s differential-routing guidance and include the required terminations to maintain signal integrity and effective receiver deskew operation.
Recomendado
Embedded Human-Machine Interface
The DS90CF388VJD is appropriate for an embedded human-machine-interface panel that requires a compact electrical link between a controller board and a larger display assembly. Eight LVDS channels provide the bandwidth needed for dual-pixel color and blanking-period control signaling, while the receiver’s plus or minus one-bit-time deskew compensates propagation differences introduced by routed cables and interconnects. The design must place the receiver in the signal path and maintain continuous differential impedance from transmitter to panel. System verification should include worst-case cable length, connector variation, clock rate, and display timing.
Recomendado
Video Processing Module
The DS90CF388VJD can provide the panel-facing LVDS receiver function in a video-processing module that accepts parallel CMOS/TTL data from a host-side transmitter and recovers a dual-pixel display stream. Its eight-lane architecture supports SVGA-through-QXGA panels, and control signals are embedded during blanking so they can travel with the associated video timing. Compared with routing the original 48-bit parallel bus across the complete system, the serialized LVDS link can reduce conductor count and simplify harness integration. Differential routing, grounding, cable qualification, and receiver termination must follow the manufacturer’s reference implementation.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para DS90CF388VJD — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | DS90CF388VJDX | DS90CF388VJD/NOPB |
|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 100-TQFP (14x14) | 100-TQFP (14x14) - same footprint | 100-TQFP (14x14) - same footprint |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V |
| Device Function | Dual-pixel LVDS receiver | Dual-pixel LVDS receiver | Dual-pixel LVDS receiver |
| Maximum Clock Rate | 80 MHz | 80 MHz | 80 MHz |
| Supported Resolutions | SVGA through QXGA | SVGA through QXGA | SVGA through QXGA |
| Receiver Deskew | plus or minus 1 LVDS data-bit time | plus or minus 1 LVDS data-bit time | plus or minus 1 LVDS data-bit time |
| LVDS Data Lane Count | 8 streams | 8 streams | 8 streams |
| Transmitter Data Width | 48 bits, dual-pixel 24-bit color | 48 bits, dual-pixel 24-bit color | 48 bits, dual-pixel 24-bit color |
| Display Interface Specification | OpenLDI | OpenLDI | OpenLDI |
Principais diferenciais
- Direct receiver-side match for the DS90C387 transmitter architecture (vs DS90CF388VJDX)
- Lead-free ordering designation preserves the original device architecture (vs DS90CF388VJD/NOPB)
- Native dual-pixel deskew supports unequal channel arrival time (vs DS90CF388VJDX)
Notas de projeto
Route each LVDS pair as a continuous differential path with matched impedance and symmetrical geometry. Avoid changing pair spacing unnecessarily, add no unterminated stubs, and keep the receiver positioned according to the signal flow. The device can deskew plus or minus one LVDS data-bit time, but deskew does not correct excessive loss, impedance discontinuities, or connector returns caused by poor layout.
Use the termination and input-protection arrangement shown in the manufacturer’s recommended application circuit, and account for connector and cable parasitics at the maximum operating clock rate of 80 MHz. Validate differential input voltage, common-mode range, channel-to-channel skew, and loss across the intended cable length. Receiver deskew corrects timing offset, not attenuation or noise outside the supported signal amplitude.
Do not treat the DS90CF388AVJD as an automatic substitute: the available comparison notes indicate similar functions but potentially different principal parameters and circuit structure. Likewise, verify the exact ordering code before using DS90CF388VJDX or DS90CF388VJD/NOPB. Confirm package, exposed thermal-pad requirements, pin assignments, and lifecycle status against current Texas Instruments documentation before releasing a replacement to production.
Informações de conformidade
The NOPB designation identifies a lead-free ordering option, but no formal RoHS, REACH, AEC-Q100, halogen-free, or conflict-minerals statement appears in the cited product information.