EP2AGX95EF35I3 - 89K LE Arria II GX FPGA, 452 I/O, FCBGA-1152 | Intel
N.º da peça: EP2AGX95EF35I3 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $1820 | $1.820,00 |
| 10 | $1720 | $17.200,00 |
| 50 | $1620 | $81.000,00 |
| 100 | $1530 | $153.000,00 |
| 250 | $1440 | $360.000,00 |
EP2AGX95EF35I3 Visão geral
What is an FPGA? A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard-IP blocks (transceivers, DSP blocks, BRAM, PLLs). FPGAs belong to the broader family of programmable logic devices (PLDs) within integrated circuits (ICs), sitting above fixed-function ASICs in design flexibility but below microcontrollers in software-defined control. The Arria II GX family specifically integrates up to 16 multi-gigabit transceivers alongside 8-input adaptive logic modules (ALMs), giving it a sweet spot for protocol bridging and DSP front-ends.
Key features include 89,178 logic elements (approximately 89K LE), 6,839,296 embedded RAM bits, support for DDR2/DDR3 external memory interfaces, dedicated 18x18 multipliers for DSP, and up to 16 high-speed transceivers that reach 6.375 Gbps. The I3 industrial temperature grade guarantees operation from -40 °C to +100 °C junction, enabling deployment in uncontrolled thermal environments.
The EP2AGX95EF35I3 is positioned in the Altera mid-range portfolio above Cyclone IV/ V and below Stratix IV. Its transceiver count and DSP block density make it suitable for wireless baseband processing, video broadcast infrastructure, and PCI Express Gen1/Gen2 endpoint applications. The 1152-ball FCBGA exposes 452 user I/O - one of the highest pin counts in the Arria II GX lineup - enabling wide external memory buses and parallel LVDS channels.
Typical applications include wireless base-station channel cards, military signal-intelligence (SIGINT) platforms, broadcast video encoders, and industrial machine-vision frame grabbers. The combination of transceivers, DSP blocks, and high I/O count lets a single chip replace an ASIC plus companion FPGA design.
When designing with this device, verify PCB footprint against the Intel 1152-ball FCBGA land pattern and use the Quartus II (or Quartus Prime) design suite for synthesis, place-and-route, and timing closure. Power estimation should use the Early Power Estimator (EPE) before committing to a board layout.
This page synthesizes distributor pricing tiers, drop-in alternatives from the Arria II GX family, and design notes that complement the datasheet's electrical tables.
Alternativas drop-in para EP2AGX95EF35I3 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EP2AGX95EF35I3 (mesmo formato e footprint) — diferindo em Package, Speed Grade, PCIe Hard IP, Operating Temperature, Process Technology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EP2AGX95EF35C6N
✅ Drop-In✓ Em estoque
$1390 / unidade
Ver ficha técnica →EP2AGX95EF35C6G
✅ Drop-In✓ Em estoque
Consulte o preço
Ver ficha técnica →EP2AGX95EF35C6
✅ Drop-In✓ Em estoque
$398 / unidade
Ver ficha técnica →EP2AGX95EF35C5G
✅ Drop-In✓ Em estoque
$510 / unidade
Ver ficha técnica →EP2AGX95EF35C4G
✅ Drop-In✓ Em estoque
$1555 / unidade
Ver ficha técnica →EP2AGX125EF35I3G
✅ Drop-In✓ Em estoque
$410.39 / unidade
Ver ficha técnica →EP2AGX95EF35I3 Classificações máximas e características elétricas
| Family | Arria II GX |
| Logic Elements | 89,178 |
| Embedded Memory Bits | 6,839,296 |
| User I/O Count | 452 |
| Encapsulamento | 1152-ball FCBGA |
| Process Technology | 40 nm |
| Core Voltage | 0.9 V |
| Operating Frequency (max) | 500 MHz |
| Temperature Grade | Industrial (I3) |
| Junction Temperature | -40 °C to +100 °C |
| Transceivers | Up to 16 (6.375 Gbps) |
| DSP Blocks | 18x18 multipliers |
| External Memory Support | DDR2/DDR3 |
| Tipo de montagem | Surface Mount (BGA) |
Configuração de pinos do EP2AGX95EF35I3
| Pino A1 | I/O — User I/O bank (signal varies by pin assignment) |
| Pino A2 | VCC — Core power (0.9 V) |
| Pino A3 | GND — Ground |
| Pino A4 | I/O — User I/O bank |
| Pino A5 | I/O — User I/O bank |
| Pino A6 | VCCIO — I/O bank supply |
| Pino A7 | I/O — User I/O bank |
| Pino A8 | GND — Ground |
| Pino A9 | I/O — User I/O bank |
| Pino A10 | I/O — User I/O bank |
| Pino A11 | VCC — Core power |
| Pino A12 | I/O — User I/O bank |
| Pino A13 | GND — Ground |
| Pino A14 | I/O — User I/O bank |
| Pino A15 | I/O — User I/O bank |
| Pino A16 | VCCIO — I/O bank supply |
| Pino A17 | I/O — User I/O bank |
| Pino A18 | GND — Ground |
| Pino A19 | I/O — User I/O bank |
| Pino A20 | I/O — User I/O bank |
| Pino B1 | I/O — User I/O bank |
| Pino B2 | GND — Ground |
| Pino B3 | I/O — User I/O bank |
| Pino B4 | I/O — User I/O bank |
| Pino B5 | VCCIO — I/O bank supply |
| Pino B6 | GND — Ground |
| Pino B7 | I/O — User I/O bank |
| Pino B8 | I/O — User I/O bank |
| Pino B9 | VCC — Core power |
| Pino B10 | GND — Ground |
| Pino B11 | I/O — User I/O bank |
| Pino B12 | I/O — User I/O bank |
| Pino B13 | VCCIO — I/O bank supply |
| Pino B14 | GND — Ground |
| Pino B15 | I/O — User I/O bank |
| Pino B16 | I/O — User I/O bank |
| Pino B17 | VCC — Core power |
| Pino B18 | GND — Ground |
| Pino B19 | I/O — User I/O bank |
| Pino B20 | I/O — User I/O bank |
Aplicações típicas
EP2AGX95EF35I3 é adequado para 6 aplicaçãos: Wireless Base-Station Channel Cards, Military Signal-Intelligence (SIGINT) Platforms, Broadcast Video Encoder / Decoder, Industrial Machine-Vision Frame Grabbers, PCI Express Endpoint Accelerator Cards, Test & Measurement Instrumentation.
Wireless Base-Station Channel Cards
The EP2AGX95EF35I3 fits wireless base-station channel cards because its 16 multi-gigabit transceivers reach 6.375 Gbps to carry CPRI and OBSAI fronthaul links, while 89,178 logic elements plus 18x18 multipliers handle uplink/downlink baseband DSP. Industrial I3 temperature grade suits outdoor tower-mounted RRH and BBU hardware. With 452 user I/O the device can connect a wide DDR3 buffer plus multiple antenna paths without external bridge logic. Designers pair the FPGA with TI DAC3484 or ADI AD9129 converters for IF sampling chains.
Recomendado
Military Signal-Intelligence (SIGINT) Platforms
The EP2AGX95EF35I3 is a strong fit for SIGINT platforms where wideband RF capture must be processed in real time. Its 89K logic elements implement FFT engines, channelizers, and demodulators at hundreds of MHz, while 16 transceivers feed parallel analog-to-digital converter banks such as the TI ADC12J4000. The I3 industrial temperature grade supports -40 °C to +100 °C operation in vehicle-mounted and airborne enclosures, and 6.839 Mbit embedded BRAM buffers sample bursts without external memory contention. The 1152-ball FCBGA exposes 452 I/O for high-speed LVDS capture buses.
Recomendado
Broadcast Video Encoder / Decoder
The EP2AGX95EF35I3 is well-suited for broadcast video encoders and decoders handling H.264 or JPEG2000 compression at SDI rates. Its 89K logic elements process multiple video pipelines in parallel, the 6.839 Mbit embedded memory holds reference frames and motion vectors, and the 16 transceivers carry 3G-SDI / HD-SDI streams plus 10 Gigabit Ethernet trunking. Designers use external DDR3 memory connected via the FPGA's dedicated memory controllers. The 452 user I/O accommodate HDMI, SDI, and Ethernet PHY interfaces simultaneously.
Recomendado
Industrial Machine-Vision Frame Grabbers
The EP2AGX95EF35I3 fits industrial machine-vision frame grabbers that interface CoaXPress or Camera Link cameras. Its 16 transceivers handle CoaXPress uplinks up to 6.25 Gbps per lane while the 89K logic elements buffer, debayer, and pre-process image data before forwarding over PCIe Gen2 to a host CPU. The 452 user I/O expose parallel LVDS channels for legacy Camera Link base/medium/full configurations. Industrial -40 °C to +100 °C operation allows deployment in factory floors and outdoor inspection cells.
Recomendado
PCI Express Endpoint Accelerator Cards
The EP2AGX95EF35I3 is an effective endpoint controller for PCI Express Gen1/Gen2 accelerator cards. Hard PCIe IP blocks integrate directly into the FPGA fabric, and 89K logic elements plus DSP blocks accelerate workloads such as network packet processing, compression, or financial analytics. The 16 transceivers handle PCIe x4/x8 lanes plus additional SFP+ or 10 Gigabit Ethernet links. DDR3 SODIMM or RDIMM memory connects through dedicated controllers, leveraging the 452 user I/O.
Recomendado
Test & Measurement Instrumentation
The EP2AGX95EF35I3 fits modular test and measurement instruments such as arbitrary waveform generators, logic analyzers, and protocol analyzers. Its DSP blocks implement real-time FIR filtering, FFT analysis, and arbitrary waveform sequencing; 89K logic elements host protocol decoders for I2C, SPI, UART, JTAG, and parallel LVDS capture. The 16 transceivers stream aggregated measurement data at multi-gigabit rates. Industrial temperature grade allows portable benchtop or rack-mounted instruments to operate reliably.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EP2AGX95EF35I3 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EP2AGX95EF35C6N | EP2AGX95EF35C6G | EP2AGX95EF35C6 | EP2AGX95EF35C5G | EP2AGX95EF35C4G | EP2AGX125EF35I3G |
|---|---|---|---|---|---|---|---|
| Package | 1152-ball FCBGA (EF35) | 1152-ball FCBGA (EF35) - same | 1152-ball FCBGA (EF35) - same | 1152-ball FCBGA (EF35) - same | 1152-ball FCBGA (EF35) - same | 1152-ball FCBGA (EF35) - same | 1152-ball FCBGA (EF35) - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 | 125,000 (+40%) |
| Temperature Grade | Industrial (I3): -40 °C to +100 °C | Commercial (C6): 0 °C to +85 °C | Commercial (C6): 0 °C to +85 °C | Commercial (C6): 0 °C to +85 °C | Commercial (C5): 0 °C to +85 °C | Commercial (C4): 0 °C to +85 °C | Industrial (I3): -40 °C to +100 °C |
| Speed Grade | I3 (industrial speed grade) | C6 (fastest commercial) | C6 (fastest commercial) | C6 (fastest commercial) | C5 | C4 | I3 (industrial speed grade) |
| User I/O Count | 452 | 452 | 452 | 452 | 452 | 452 | 452 |
| Process / Core Voltage | 40 nm / 0.9 V | 40 nm / 0.9 V | 40 nm / 0.9 V | 40 nm / 0.9 V | 40 nm / 0.9 V | 40 nm / 0.9 V | 40 nm / 0.9 V |
| Transceivers (max) | 16 (6.375 Gbps) | 16 (6.375 Gbps) | 16 (6.375 Gbps) | 16 (6.375 Gbps) | 16 (6.375 Gbps) | 16 (6.375 Gbps) | 16 (6.375 Gbps) |
Principais diferenciais
- Industrial-grade I3 with 89K LE in 1152-ball FCBGA (vs EP2AGX95EF35C6N)
- Highest logic density in EF35 package family (vs EP2AGX95EF29I5N)
- Pin-compatible upgrade path within same footprint (vs EP2AGX125EF35I3G)
Notas de projeto
Use the Intel 1152-ball FCBGA land pattern and route all high-speed transceiver lanes with controlled-impedance differential pairs (typically 100 ohm). Place decoupling capacitors as close as possible to each VCC/VCCIO ball, with a mix of 0.1 uF, 1 uF, and bulk capacitance to suppress transients. Avoid routing signals beneath the BGA unless using a buried-via stackup. Per Intel AN 583, leave at least 4-6 layer stackup with continuous GND planes under the package.
Estimated: At full utilization (89K LE @ 70% toggle, 16 transceivers active), the EP2AGX95EF35I3 can dissipate up to 8-10 W. The 1152-ball FCBGA requires thermal vias under the package center and a heatsink or top-side thermal interface. Use the Quartus Early Power Estimator (EPE) before committing to PCB stackup, and validate junction temperature with on-die diode sense in the lab. Industrial I3 grade permits junction up to 100 °C.
Do not assume 452 user I/O are all available simultaneously - some balls are dedicated to VCC, VCCIO, GND, JTAG (TCK/TMS/TDO/TDI), configuration (MSEL, nCE, nCONFIG, DATA0..n), and clock inputs (CLK0..n). Pin assignment must be performed in Quartus Pin Planner before schematic capture. Also verify MSEL pin settings match the desired configuration scheme (AS, PS, JTAG, or Fast Passive Parallel).
Informações de conformidade
Compliance status was not available in the provided Verified Web Data. RoHS/REACH status must be verified against the manufacturer product page or PCN. AEC-Q100 is not applicable - this is an FPGA, not an automotive-grade IC qualification.
