EP2S90F1508C3 - Stratix II 90K LE FPGA, 902 I/O FCBGA-1508 | Intel
N.º da peça: EP2S90F1508C3 ⚠ Última compra| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $4959.18 | $4.959,18 |
| 5 | $4760.81 | $23.804,05 |
| 10 | $4463.26 | $44.632,60 |
| 25 | $4091.32 | $102.283,00 |
| 100 | $3719.39 | $371.939,00 |
EP2S90F1508C3 Visão geral
What is a Stratix II FPGA? An FPGA (Field-Programmable Gate Array) is a reconfigurable logic device that combines programmable logic blocks, programmable interconnect, and dedicated silicon resources such as block RAM, DSP blocks, multipliers, and high-speed transceivers. The Stratix II family introduced the ALM (Adaptive Logic Module), a successor to the classic 4-input LUT architecture, capable of implementing any function of up to 7 inputs and offering finer-grained logic packing. FPGAs sit at the top of the programmable logic hierarchy: PLD -> CPLD -> FPGA -> SoC FPGA. Within the Stratix II family, the EP2S90 is the high-density tier beneath the EP2S130 and EP2S180.
Key differentiating features of the EP2S90F1508C3 include 90960 logic elements, 4548488 RAM bits, 384 (approximate) 18x18 multipliers via DSP blocks, twelve PLLs for clock management, and 1.2 V core operation. The device supports configuration via JTAG and serial/parallel configuration schemes, and includes dedicated hardware for dynamic reconfiguration, signal integrity, and partial reconfiguration. The "C3" speed grade denotes a commercial temperature grade with the slowest speed bin in the family, while "F1508" identifies the 1508-ball FCBGA package.
From an architecture standpoint, the Stratix II device employs a heterogeneous routing fabric with row/column interconnect and tri-matrix memory blocks (M512, M4K, M-RAM), giving designers a flexible mix of small and large memory resources. The DSP blocks support 9-bit, 18-bit, and 36-bit word widths and can be cascaded for high-precision filters and FFTs.
Typical applications include telecom baseband processing, high-speed image and video pipelines, ASIC prototyping, test and measurement instrumentation, and high-performance DSP coprocessors. Designers choose the EP2S90F1508C3 when the design requires more logic, memory, and DSP than mid-density FPGAs can provide.
When designing with this device, plan PCB layout carefully - the 1508-ball FCBGA at 1.0 mm pitch demands microvia or HDI PCB technology, controlled-impedance routing for high-speed signals, and a multi-layer stackup with solid ground/power planes. Power decoupling must follow the Stratix II pin connection guidelines for VCCINT, VCCIO, VCCA, and VTT rails.
This page synthesizes distributor inventory, same-brand drop-in alternatives drawn from the Stratix II family, and practical design notes that complement the manufacturer datasheet.
Alternativas drop-in para EP2S90F1508C3 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EP2S90F1508C3 (mesmo formato e footprint) — diferindo em Package, Speed Grade, Logic Elements, Total RAM Bits, Mounting Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EP2S90F1508C3N
✅ Drop-In✓ Em estoque
$3200 / unidade
Ver ficha técnica →EP2S90F1508C4
✅ Drop-In✓ Em estoque
$1320 / unidade
Ver ficha técnica →EP2S90F1508C5
✅ Drop-In✓ Em estoque
$2590 / unidade
Ver ficha técnica →EP2S130F1508C3
✅ Drop-In✓ Em estoque
$1350 / unidade
Ver ficha técnica →EP2S130F1508C3N
✅ Drop-In✓ Em estoque
$270 / unidade
Ver ficha técnica →EP2S180F1508C3
✅ Drop-In✓ Em estoque
Consulte o preço
Ver ficha técnica →EP2S180F1508C3N
✅ Drop-In✓ Em estoque
$1200 / unidade
Ver ficha técnica →EP2S90F1508C3 Classificações máximas e características elétricas
| Family | Stratix II |
| Logic Elements | 90960 |
| Total RAM Bits | 4520488 |
| Number of LABs/CLBs | 4548 |
| Number of I/O | 902 |
| Number of GPIO | 902 |
| Voltage - Supply | 1.2 V |
| Temperatura de operação | 0C to +85C (commercial) |
| Tipo de montagem | Surface Mount |
| Encapsulamento | 1508-BBGA, FCBGA |
| Speed Grade | C3 (commercial, slowest) |
| Process Technology | 90 nm CMOS |
| DSP Blocks | 12 |
| Maximum Frequency | 816.99 MHz (per third-party listing) |
Guia de Configuração de Pinos do EP2S90F1508C3 1508-bbga, fcbga
Configuração de pinos para EP2S90F1508C3 (pacote 1508-bbga, fcbga). Este CI digital inclui GPIO, interfaces de comunicação (UART, SPI, I2C) e pinos de alimentação. Consulte o datasheet do fabricante para funções alternativas dos pinos e opções de configuração. Essencial para projeto de sistemas embarcados e layout de PCB.
Nenhum dado detalhado de pinagem disponível para EP2S90F1508C3.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
EP2S90F1508C3 é adequado para 6 aplicaçãos: Telecom Baseband Processing, ASIC Prototyping, High-Performance DSP Coprocessor, Test and Measurement Instrumentation, High-Speed Image and Video Pipeline, Industrial Control and Automation.
Telecom Baseband Processing
The EP2S90F1508C3 fits telecom baseband workloads thanks to 90960 logic elements, 12 dedicated DSP blocks (up to 384 18x18 multipliers), and 4.5 Mbit of embedded RAM, providing headroom for channel cards, FEC codecs, and packet-processing datapaths. With 902 user I/O the device can fan out to multiple external RapidIO or parallel LVDS links, while twelve PLLs deliver low-jitter clocks to the SERDES and DSP paths. Compared with a fixed-function ASIC, the FPGA-based approach lets carriers deploy late firmware updates for new air-interface revisions.
Recomendado
ASIC Prototyping
Engineers use the EP2S90F1508C3 as an ASIC prototype target because the 90960 LE plus 4.5 Mbit of block RAM comfortably fits mid-complexity SoC designs while the 1508-ball FCBGA exposes enough I/O for peripheral emulation. Twelve PLLs and dedicated DDR-style memory interfaces simplify connection to external SRAM, DDR, and QDR memories, while 902 GPIO make it easy to break out legacy buses. The C3 speed grade is generally sufficient for prototype verification at 50-100 MHz, and faster C4/C5 speed grades are pin-compatible.
Recomendado
High-Performance DSP Coprocessor
The 12 DSP blocks in the EP2S90F1508C3 implement up to 384 18x18 multipliers, enabling single-chip FFT, FIR, and matrix accelerators for radar, sonar, and software-defined radio pipelines. Combined with 4.5 Mbit of RAM, the device can hold working data sets and coefficient tables on-chip, eliminating costly external memory accesses. With 902 I/O the part exposes multiple parallel data paths to ADCs and DACs, and twelve PLLs supply the low-jitter sampling clocks needed by wideband converters. Drop-in density upgrades to EP2S130 or EP2S180 in the same F1508 package scale throughput linearly.
Recomendado
Test and Measurement Instrumentation
Test equipment vendors value the EP2S90F1508C3 for its 902 I/O - enough to drive many parallel measurement channels simultaneously - and 4.5 Mbit of on-chip RAM to buffer sample streams before DMA to the host. The ALM-based fabric of Stratix II provides efficient state-machine and packet-builder logic, while twelve PLLs feed multiple clock domains for mixed-rate acquisition. Designers can hold the bitstream in flash and reconfigure between product variants, reducing SKU complexity. Lead-free EP2S90F1508C3N is preferred for new compliance-driven test platforms.
Recomendado
High-Speed Image and Video Pipeline
The EP2S90F1508C3 supports multi-stream video processing with 90960 logic elements to drive multiple camera/display pipelines and 4.5 Mbit of embedded RAM to buffer line and frame data on-chip. Its 902 I/O comfortably host multiple LVDS-based camera links (e.g., Channel Link, FPD-Link) plus HDMI/DVI outputs. Twelve DSP blocks accelerate pixel-level operations such as color-space conversion, sharpening, and gamma correction. For 4K or multi-camera systems, the EP2S130F1508C3 or EP2S180F1508C3 in the same F1508 footprint give headroom.
Recomendado
Industrial Control and Automation
Industrial controller designers use the EP2S90F1508C3 to consolidate deterministic logic, motion-control loops, and protocol bridging on a single chip. The 90960 logic elements implement multi-axis motion controllers, while the 12 DSP blocks execute PID and state-space compensators at high sample rates. The 902 I/O fan out to stepper drivers, encoders, and EtherCAT/PROFIBUS bridges, and twelve PLLs drive synchronized PWMs to multiple axes. For new industrial designs in 2026, however, designers should evaluate Cyclone V or Cyclone 10 LP because Stratix II is in last-time-buy status.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EP2S90F1508C3 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EP2S90F1508C3N | EP2S90F1508C4 | EP2S90F1508C5 | EP2S130F1508C3 | EP2S180F1508C3 |
|---|---|---|---|---|---|---|
| Package | 1508-FCBGA | 1508-FCBGA | 1508-FCBGA | 1508-FCBGA | 1508-FCBGA | 1508-FCBGA |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 90960 | 90960 | 90960 | 90960 | 132560 | 179400 |
| RAM Bits | 4520488 | 4520488 | 4520488 | 4520488 | 6747840 | 9388032 |
| Speed Grade | C3 (slowest) | C3 | C4 | C5 | C3 | C3 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| RoHS / Lead-free | Unknown (pre-N suffix) | Yes (lead-free) | Unknown | Unknown | Unknown | Unknown |
Principais diferenciais
- Highest I/O count in the EP2S90 family (vs EP2S90F1020C3 (1020-ball package variant))
- Same die across the F1508 package family - true drop-in scalability (vs EP2S130F1508C3 and EP2S180F1508C3 in the same F1508 package)
- 12 DSP blocks at C3 speed grade still useful for cost-sensitive designs (vs EP2S90F1508C5 (fastest speed grade))
- Backward-compatible configuration scheme with Quartus II (vs Xilinx Virtex-4 Pro (same era competitor))
Notas de projeto
The EP2S90F1508C3 uses a 1508-ball FCBGA at 1.0 mm pitch. Per the Stratix II pin connection guidelines, the PCB stackup must support microvias (laser-drilled or photo-defined) and a fine-pitch escape routing pattern under the BGA. Use a 1-2-1 or 1-3-1 HDI stackup with paired ground/power planes. Stitching vias should be placed within 1 mm of every high-speed signal via to maintain return-path continuity. Solid reference planes under the BGA are mandatory for DDR/PLL performance.
Estimated: for the EP2S90F1508C3 at typical utilization (50% LE, 50% RAM, 50% DSP) the Stratix II PowerPlay estimator gives a core power around 5-8 W and total device power (including I/O toggling at 100 MHz) around 10-15 W. Designers must supply VCCINT (1.2 V), VCCIO (1.5/1.8/2.5/3.3 V banked), VCCA (1.2 V analog), and VTT for DDR termination rails, with bulk + ceramic decoupling per the Stratix II device handbook. Total decoupling budget is 30-50 capacitors per supply rail.
The 1508-ball FCBGA has an exposed die that must be thermally attached to a heatsink or cold plate. Estimated junction-to-ambient thermal resistance without heatsink is in the 15-20 C/W range, so at 15 W total device power the junction rises 225-300 C above ambient - well above the 125 C maximum. A forced-air heatsink (1-2 C/W) plus thermal interface material is required for typical workloads. Case temperature must be measured via on-die diode (TempSense) and logged for reliability.
Common pitfalls with EP2S90F1508C3 designs include: (1) forgetting to release all unused I/O banks to a defined logic level to avoid floating inputs; (2) mixing C3 bitstreams with C4/C5 boards because speed-grade bitstreams are NOT interchangeable; (3) underprovisioning VCCIO bank current when many SSTL/HSTL outputs toggle simultaneously; (4) assuming the EP2S90F1508C3 and EP2S130F1508C3 share bitstreams (they do not - Quartus II must rebuild for the new device); (5) using lead-free (N-suffix) boards with non-N parts may violate RoHS assembly profiles.
DDR/DDR2 memory interfaces on the EP2S90F1508C3 must follow the Stratix II External Memory Interface Handbook. Use DQ-DQS group matching within +/-25 ps, OCT (on-chip termination) calibrated at power-up, and dynamic phase-shift on DQS to capture write data. For LVDS channels, the receiver skew margin should be measured on the bench with a 2-Tap pattern; target at least 0.4 UI margin at 1 Gbps. Source-synchronous strobe signals should be deskewed via PLL feedback paths, not free-running PLL outputs.
Informações de conformidade
RoHS/lead-free status not present in the verified web data. The N-suffix variant EP2S90F1508C3N is widely understood to be lead-free; the base EP2S90F1508C3 may pre-date RoHS assembly directives. Always confirm with the actual distributor CoC before production use. AEC-Q100 not applicable for FPGAs.