Altera

EP3SE260F1152C3NES - Stratix III E FPGA 255K LE 1152-FBGA | Altera

N.º da peça: EP3SE260F1152C3NES ⚠ Última compra

Em estoque Enviado em 1 a 3 dias úteis

1.1 V Vdss 1152-ball FBGA (FineLine BGA) Package 500 MHz Speed 16,672,768 Memory

A partir de $2120 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-09

Preços por volume

Qtd.	Preço unitário	Total
1	$2850	$2.850,00
10	$2680	$26.800,00
100	$2450	$245.000,00
500	$2280	$1.140.000,00
1.000	$2120	$2.120.000,00

ℹ️ Todos os preços estão em USD

Ver datasheet (PDF) Ver alternativas

Quantidade

EP3SE260F1152C3NES Visão geral

The Altera (Intel) EP3SE260F1152C3NES is a high-density Stratix III Enhanced family Field Programmable Gate Array (FPGA) built on a 65 nm process, delivering 255,000 logic elements, 744 user I/Os, and an operating frequency up to 500 MHz in a 1152-ball FineLine BGA (FBGA) package. Core voltage is 1.1 V and the device targets high-performance digital signal processing, ASIC prototyping, and high-bandwidth data-path applications.

An FPGA (Field Programmable Gate Array) is a programmable logic device containing an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and high-speed transceivers interconnected by a programmable routing fabric. FPGAs sit in the broader hierarchy of programmable logic devices (PLDs) -> programmable logic -> semiconductor ICs, and are widely used for parallel processing, hardware acceleration, and rapid prototyping where fixed-function ASICs are too costly or inflexible.

Key features include 16,672,768 bits of embedded memory, 10,200 LABs (Logic Array Blocks), 768 18x18 multipliers, 12 PLLs, and 744 maximum user I/Os. The device integrates 4 hard memory controllers and 4 hard PCI Express hard IP blocks, with support for external memory interfaces including DDR3, DDR2, DDR, QDRII+, and RLDRAM2. Speed grade is -3 (faster), logic element count is 255,000, and the design is built on TSMC's 65 nm low-power process technology.

Architecturally, the Stratix III E family adopts an adaptive logic module (ALM) based on an 8-input fracturable LUT, which improves logic packing density versus older 4-input LUT architectures. The transceiver subsystem is augmented with dedicated hard IP for PCIe Gen1/Gen2, making the device suitable for serial connectivity bridging. Multi-track routing and TriMatrix on-chip memory with error correction code (ECC) support ensure deterministic timing closure for high-performance designs.

Typical applications include high-speed data acquisition, ASIC prototyping, software-defined radio (SDR), video processing pipelines, military/aerospace signal processing, and high-end communications infrastructure. The dense logic and high I/O count also suit multi-protocol bridging and high-speed serial backplane designs.

When designing with this device, ensure proper power-decoupling network design with bulk, mid-frequency, and high-frequency ceramic capacitors, and pay close attention to the PCB BGA breakout routing. Signal integrity and controlled-impedance differential pairs are required for the high-speed transceivers. The Quartus II design toolchain is used for synthesis, place-and-route, and timing closure.

This page synthesizes distributor pricing, parametric alternatives, and practical design notes not found in the standalone Altera datasheet, providing engineers with a one-stop reference for sourcing and design-in decisions.

Alternativas drop-in para EP3SE260F1152C3NES — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EP3SE260F1152C3NES (mesmo formato e footprint) — diferindo em Package, Speed Grade, Series, Process Technology, Family.

EP3SE110F1152C3

Altera

Package: 1152-BBGA, FCBGA

Speed Grade: C3 (commercial, slower speed grade)

Family: Stratix III E

Comparar com EP3SE260F1152C3NES →

EP3SE260F1152C2

Intel

Package: 1152-ball FC-FBGA (Flip Chip)

Speed Grade: C2 (commercial)

Series: Stratix® III E

Comparar com EP3SE260F1152C3NES →

EP3SE260F1152C2G

Altera

Package: 1152-BBGA, FCBGA (FineLine BGA)

Speed Grade: C2 (commercial)

Series: EP3SE260

Comparar com EP3SE260F1152C3NES →

EP3SE260F1152C2N

Intel

Family: FPGA - Field Programmable Gate Array

Comparar com EP3SE260F1152C3NES →

EP3SE260F1152C3

Intel

Package: 1152-ball FCBGA (Flip-Chip BGA)

Speed Grade: C3

✅ Drop-In

Altera

📦 1152-FBGA (F1152)

Stratix III E · 107,500 · 4,300 · 43,040 · 8,936,448 · 744 · 800 MHz · 0.9 V

✓ Em estoque

$3200 / unidade

Ver ficha técnica →

EP3SE260F1152C3NES Classificações máximas e características elétricas

Manufacturer	Altera (now Intel FPGA)
Series	Stratix III E
Family	Stratix III Enhanced
Logic Elements (LE)	255,000
Embedded Memory Bits	16,672,768
Logic Array Blocks (LABs)	10,200
Number of I/Os	744
Maximum Operating Frequency	500 MHz
Process Technology	65 nm
Core Supply Voltage	1.1 V
Number of 18x18 Multipliers	768
Number of PLLs	12
Package Type	1152-ball FBGA (FineLine BGA)
Pin/Package Designator	F1152
Speed Grade	-3 (faster)
Hard Memory Controllers	4
Hard PCIe Blocks	4
External Memory Interface	DDR3, DDR2, DDR, QDRII+, RLDRAM2
Operating Temperature Grade	Commercial
Tipo de montagem	Surface Mount
Status RoHS	Compliant
Lead-Free	Yes

Guia de Configuração de Pinos do EP3SE260F1152C3NES f1152

Configuração de pinos para EP3SE260F1152C3NES (pacote f1152). Este CI digital inclui GPIO, interfaces de comunicação (UART, SPI, I2C) e pinos de alimentação. Consulte o datasheet do fabricante para funções alternativas dos pinos e opções de configuração. Essencial para projeto de sistemas embarcados e layout de PCB.

Diagrama de pinagem do pacote f1152 para EP3SE260F1152C3NES

Nenhum dado detalhado de pinagem disponível para EP3SE260F1152C3NES.

Consulte a ficha técnica para a configuração completa dos pinos.

Aplicações típicas

EP3SE260F1152C3NES é adequado para 6 aplicaçãos: High-Speed Data Acquisition Systems, ASIC Prototyping and Emulation, Software-Defined Radio (SDR) Baseband, Video Processing and Image Pipeline, Military and Aerospace Signal Processing, High-Speed Communications Infrastructure.

📊

High-Speed Data Acquisition Systems

The EP3SE260F1152C3NES fits high-speed data acquisition systems where 255,000 logic elements, 768 18x18 multipliers, and 16,672,768 bits of embedded memory provide the parallel processing and buffering required for multi-channel ADC capture pipelines. Its 4 hard memory controllers and 4 hard PCIe Gen1/Gen2 IP blocks enable direct DDR3 buffer storage and high-throughput host upload with deterministic latency, while 744 user I/Os accommodate wide parallel LVDS data paths from multiple ADC chips. Place the FPGA between the ADC bank and the host CPU, with decoupling caps on every VCC pin per the Stratix III pin connection guidelines, and use TimeQuest to constrain the ADC-to-DDR3 path for sub-clock-cycle setup/hold margin.

Recomendado

EP4SE530F43C3N (Higher-density Stratix IV E upgrade for larger acquisition systems) AD9255-105 (14-bit 105 MSPS ADC commonly paired with Stratix III FPGA)

🔬

ASIC Prototyping and Emulation

ASIC prototyping and emulation is a primary use case for the EP3SE260F1152C3NES, where 255K logic elements can map sizeable ASIC netlists partitioned across multiple FPGAs via TDM or multi-FPGA partitioning flows. The 1152-ball FBGA provides 744 user I/Os for inter-FPGA hand-off channels, and the embedded TriMatrix memory supports large trace buffers for design verification. Engineers typically use Synopsys Certify or Mentor Graphics Nitro to partition ASIC RTL onto the device and validate at 50-200 MHz target ASIC clock. Quartus II's LogicLock regions and chip-planner help isolate partition boundaries for repeatable bring-up across multiple prototyping boards.

Recomendado

📡

Software-Defined Radio (SDR) Baseband

Software-defined radio baseband processing benefits from the EP3SE260F1152C3NES's 768 18x18 multipliers, which deliver the multiply-accumulate throughput required for wideband digital down-conversion (DDC), digital up-conversion (DUC), and channelization. The 16,672,768 bits of embedded memory serve as FFT window buffers and channel coefficient storage, while the 4 hard PCIe blocks enable direct host transfer of demodulated symbols. Typical placement is between the RF front-end ADC/DAC and the host CPU, with the FPGA implementing the PHY/MAC layer. The 12 PLLs allow independent clock domains for the ADC sample rate, the FPGA fabric, and the PCIe link, simplifying mixed-clock design.

Recomendado

AD9361 (Wideband RF transceiver commonly paired with Stratix III in SDR designs) EP4SGX230KF40C2N (Stratix IV GX with integrated transceivers for higher-band SDR)

📺

Video Processing and Image Pipeline

Real-time video processing pipelines for broadcast, surveillance, and medical imaging use the EP3SE260F1152C3NES's parallel fabric to implement color-space conversion, scaling, deinterlacing, and codec pre-processing at 1080p60 and beyond. The 744 user I/Os accommodate multiple parallel video ports (BT.1120, DisplayPort aux channels, and HDMI/DVI links via external PHY), and the embedded memory serves as line/frame buffers. The 768 DSP blocks accelerate motion-estimation and deblocking filters, while the 4 hard PCIe blocks provide a low-latency path for delivering processed frames to the host codec. Quartus II's DSP Builder accelerates algorithm-to-RTL flow for these pipelines.

Recomendado

ADV7513 (HDMI transmitter PHY often paired with Stratix III for video output) EP3SE260F1152C3N · Intel

✈️

Military and Aerospace Signal Processing

Military and aerospace signal processing applications leverage the EP3SE260F1152C3NES's high logic density and embedded DSP resources for radar, electronic warfare (EW), and signals-intelligence (SIGINT) workloads. The 1152-ball FBGA package is qualified for harsh-environment board assembly, and the commercial temperature grade (0C to +85C) suits ground-based and shipboard installations; for airborne and weapons-grade applications, an I-temp or M-temp screened variant would be required. The hard PCIe blocks enable integration with modern VPX and VME host systems, while the abundant PLLs support the multi-clock architectures typical of phased-array radar front-ends. Mission-critical designs typically use Triple Modular Redundancy (TMR) implemented in fabric.

Recomendado

EP3SE110F1152I3N · Altera AD9854 (DDS synthesizer commonly paired with FPGAs in radar/EW designs)

🌐

High-Speed Communications Infrastructure

The EP3SE260F1152C3NES serves high-speed communications infrastructure applications such as multi-protocol bridging, packet processing, and 10G/40G line-card processing. Its 744 user I/Os connect to multiple SFP+/SFP cages and backplane SERDES PHYs, while the 16 Mbits of embedded memory support packet header parsing and lookup-table-driven forwarding engines. The 768 18x18 multipliers accelerate encryption/decryption and CRC offload, reducing host CPU load. The 4 hard PCIe Gen1/Gen2 blocks enable co-processing with Intel/AMD host CPUs, and the 12 PLLs support multiple independent reference clocks for synchronous Ethernet and PTP timing. Quartus II's transceiver tool kit and MegaWizard help with PHY configuration.

Recomendado

TLK10034 (10 Gbps Ethernet PHY often paired with Stratix III line cards) EP4SGX230KF40C2N (Stratix IV GX with integrated 8.5 Gbps transceivers)

Resumo dos produtos recomendados

EP4SE530F43C3N Higher-density Stratix IV E upgrade for larger acquisition systems Usado em: High-Speed Data Acquisition Systems AD9255-105 14-bit 105 MSPS ADC commonly paired with Stratix III FPGA Usado em: High-Speed Data Acquisition Systems EP3SE110F1152C3N Intel Usado em: ASIC Prototyping and Emulation EP4CGX150CF23C7N Intel Usado em: ASIC Prototyping and Emulation AD9361 Wideband RF transceiver commonly paired with Stratix III in SDR designs Usado em: Software-Defined Radio (SDR) Baseband EP4SGX230KF40C2N Stratix IV GX with integrated transceivers for higher-band SDR Usado em: Software-Defined Radio (SDR) Baseband, High-Speed Communications Infrastructure ADV7513 HDMI transmitter PHY often paired with Stratix III for video output Usado em: Video Processing and Image Pipeline EP3SE260F1152C3N Intel Usado em: Video Processing and Image Pipeline EP3SE110F1152I3N Altera Usado em: Military and Aerospace Signal Processing AD9854 DDS synthesizer commonly paired with FPGAs in radar/EW designs Usado em: Military and Aerospace Signal Processing TLK10034 10 Gbps Ethernet PHY often paired with Stratix III line cards Usado em: High-Speed Communications Infrastructure

What is the EP3SE260F1152C3NES?

The EP3SE260F1152C3NES is a high-density Altera Stratix III Enhanced family FPGA with 255,000 logic elements, 744 user I/Os, and 16,672,768 bits of embedded memory in a 1152-ball FBGA package. It is built on a 65 nm process with a 1.1 V core supply and a maximum operating frequency of 500 MHz, targeting high-performance digital signal processing and ASIC prototyping.

What is the difference between EP3SE260F1152C3NES and EP3SE260F1152C3N?

Both parts share the same Stratix III E die (255K LE) and the same 1152-ball FBGA package. The C3NES suffix variant follows Altera's standard ordering code indicating commercial temperature grade with lead-free / RoHS compliance, while C3N denotes the same die with a slightly different ordering descriptor; per the Altera ordering guide they are functionally identical drop-in parts at the same speed grade -3.

What is the package type of EP3SE260F1152C3NES?

The EP3SE260F1152C3NES is housed in a 1152-ball FineLine BGA (FBGA) package, identified by the F1152 designator. This is the largest package in the EP3SE260 family, providing 744 user I/Os for high-bandwidth parallel and serial interfaces. Per the Altera packaging manual, the F1152 package is a 35x35 mm BGA with 1.0 mm ball pitch.

What is the operating temperature range of EP3SE260F1152C3NES?

The C3 ordering code suffix indicates the commercial temperature grade of 0C to +85C junction temperature. For industrial (-40C to +100C) or military temperature grades, the suffix would be I3 or M3 respectively. Industrial and military variants may have different lead-time and pricing.

How much does the EP3SE260F1152C3NES cost?

As of 2026-09-09, the EP3SE260F1152C3NES is priced at approximately USD 2850 per unit at qty 1, with tier pricing of about USD 2680 at qty 10, USD 2450 at qty 100, USD 2280 at qty 500, and USD 2120 at qty 1000. Pricing is on the rise because the Stratix III family is in its last-time-buy phase; contact your authorized distributor for current quote.

Where can I buy the EP3SE260F1152C3NES online?

The EP3SE260F1152C3NES can be ordered from authorized distributors including DigiKey, Mouser, Ariat-Tech, Jotrin Electronics, and YIC Electronics. As of 2026-09-09, distributor stock is constrained because the part is in the last-time-buy window; lead time is typically 6-12 weeks and prices reflect end-of-life allocation. Verify RoHS and original-factory traceability before placing volume orders.

What is the lead time for the EP3SE260F1152C3NES?

As of 2026-09-09, the EP3SE260F1152C3NES lead time is approximately 6 to 12 weeks through authorized distributors, and stock is limited because the Stratix III E family is in its last-time-buy (LTB) phase. Once inventory is exhausted, no further factory production will be available, so long-life-cycle programs should secure last-build quantities now or migrate to Stratix V or Cyclone V equivalents.

Is the EP3SE260F1152C3NES in stock?

As of 2026-09-09, distributor stock of the EP3SE260F1152C3NES is limited and varies by region; Ariat-Tech, Jotrin, and YIC list small quantities, while DigiKey and Mouser may show zero or backorder status. Because the part is in its last-time-buy phase, we recommend requesting a quote immediately for production-volume needs and verifying RoHS-compliant factory original packaging.

What is the difference between EP3SE260F1152C3NES and EP3SE260F1152C4N?

Both parts are the same 255K-LE Stratix III E die in the same F1152 FBGA package, and the only difference is the speed grade suffix: -3 (faster) versus -4 (fastest). The -3 grade supports Fmax around 500 MHz, while the -4 grade pushes Fmax approximately 10-15% higher at the cost of increased power. Either is a drop-in replacement when design timing closes on the chosen speed grade.

What is the best drop-in replacement for EP3SE260F1152C3NES?

The best drop-in replacements are other EP3SE260F1152 variants with the same F1152 BGA package, such as EP3SE260F1152C3N (same -3 speed grade, slightly different ordering code), EP3SE260F1152C2N (lower -2 speed grade, drop-in for designs that close timing on -2), and EP3SE260F1152C4N (higher -4 speed grade, drop-in for performance headroom). All are pin-compatible in the same 1152-ball BGA footprint.

What are the key specifications of EP3SE260F1152C3NES that engineers should know?

The five key specifications are: 255,000 logic elements for parallel processing capacity; 16,672,768 bits of embedded memory for buffer/lookup applications; 768 18x18 multipliers for DSP throughput; 12 PLLs for flexible clock management; and 744 user I/Os plus 4 hard PCIe Gen1/Gen2 blocks for high-speed serial connectivity. Together these define the device's position in the high-density FPGA segment.

EP3SE260F1152C3NES vs EP3SE110F1152C3 - which is better for high-density designs?

The EP3SE260F1152C3NES has 255,000 logic elements versus 110,000 for the EP3SE110F1152C3, so the EP3SE260 is the better choice for high-density designs needing more LUTs, more memory, and more multipliers. Both share the same F1152 FBGA package and same speed grade, so the EP3SE110 is a drop-in cost/footprint alternative only when the design fits within 110K LE.

When should I choose EP3SE260F1152C3NES over a newer Stratix V FPGA?

Choose the EP3SE260F1152C3NES only when the design is already on Stratix III silicon, the board layout is locked to the F1152 BGA footprint, or existing IP and firmware target the Stratix III ALM architecture. For new designs, the Stratix V or Cyclone V families offer lower power, faster transceivers, and longer lifecycle support. Migrating to Stratix V typically requires IP recompile but offers significantly better cost-per-LE today.

Is the EP3SE260F1152C3NES suitable for high-speed serial interfaces?

Yes, the EP3SE260F1152C3NES includes 4 hard PCI Express Gen1/Gen2 IP blocks and supports external memory interfaces including DDR3, DDR2, DDR, QDRII+, and RLDRAM2, making it well suited for high-speed serial bridging and memory-intensive buffering. The dedicated hard IP blocks free up fabric resources for application logic and reduce design risk versus soft IP implementations.

Where can I download the EP3SE260F1152C3NES datasheet PDF?

The official Altera datasheet for the Stratix III E family (which covers the EP3SE260 device) is available from Intel's FPGA documentation archive. Third-party distributors including Ariat-Tech and YIC Electronics also host PDF copies; the Ariat-Tech datasheet URL is listed on this page. For complete device specifications, request the Stratix III Device Handbook (all volumes) from Intel's FPGA Resource Center.

What is the best Altera equivalent for the EP3SE260F1152C3NES in newer families?

The closest Altera/Intel newer-family equivalents to the EP3SE260F1152C3NES are the Stratix V E family (5SEE9 devices with similar LE count) and the Arria 10 family for lower-power applications. The Stratix V offers up to 1.1 million logic elements, 53.3 Gbps transceivers, and a 28 nm process, providing 2-3x the performance at similar or lower power. Direct pin-for-pin migration to F1152 BGA is not supported, so PCB redesign is required.

Dados de referência de engenharia para EP3SE260F1152C3NES — comparação, orientação de projeto e informações de conformidade.

Guia de seleção

Choose the EP3SE260F1152C3NES when you need 255K logic elements, 16.7 Mbits of embedded memory, 768 DSP multipliers, and 744 user I/Os in a 1152-ball FBGA package, and your design timing closes on the -3 speed grade. Choose the EP3SE260F1152C2N if your design meets timing at the slower -2 grade (approximately 15% lower Fmax) and you want the lowest unit price. Choose the EP3SE110F1152C3 if your design fits within 110K LE, 8.2 Mbits memory, and 384 DSP blocks - it is a drop-in on the same F1152 footprint with a significant cost reduction. For new designs, evaluate Stratix V E family devices for better performance-per-watt, but budget for PCB redesign since the F1152 footprint is not pin-compatible across families.

Comparação com alternativas

Parâmetro	Este produto	EP3SE260F1152C3N	EP3SE260F1152C3	EP3SE260F1152C2N	EP3SE260F1152C2G	EP3SE260F1152C2	EP3SE110F1152C3
Brand	Altera	Altera	Altera	Altera	Altera	Altera	Altera
Package	1152-FBGA (F1152)	1152-FBGA (F1152) - same	1152-FBGA (F1152) - same	1152-FBGA (F1152) - same	1152-FBGA (F1152) - same	1152-FBGA (F1152) - same	1152-FBGA (F1152) - same
Logic Elements	255,000	255,000	255,000	255,000	255,000	255,000	110,000
Speed Grade	-3 (faster)	-3	-3	-2	-2	-2	-3
Embedded Memory Bits	16,672,768	16,672,768	16,672,768	16,672,768	16,672,768	16,672,768	8,209,920
User I/Os	744	744	744	744	744	744	744
Multipliers (18x18)	768	768	768	768	768	768	384
Process Node	65 nm	65 nm	65 nm	65 nm	65 nm	65 nm	65 nm
Core Voltage	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V
Lifecycle Status	Last Time Buy	Last Time Buy	Last Time Buy	Last Time Buy	Last Time Buy	Last Time Buy	Last Time Buy

Principais diferenciais

Highest-density member of the EP3SE260 family at -3 speed grade (vs EP3SE110F1152C3)
Balanced -3 speed grade (faster) versus -2 (slower) tier (vs EP3SE260F1152C2N)
Same ordering suffix family as standard C3N commercial drop-in (vs EP3SE260F1152C3N)

Notas de projeto

The EP3SE260F1152C3NES requires a multi-rail power supply: 1.1 V core, 2.5 V or 3.0 V analog PLL supply (VCC_PLL), 1.2 V/1.5 V/1.8 V/2.5 V/3.0 V/3.3 V I/O supplies (VCCIO), and a 2.5 V/3.0 V pre-emphasis supply (VCCPD). Designers should use a power-sequencing controller to ensure core voltage rises before I/O supplies. Decoupling must follow the Stratix III pin connection guidelines with bulk, mid-frequency, and high-frequency capacitors placed adjacent to every VCC/VCCIO/VCCPD/VCC_PLL ball pair.

Estimated: at 1.1 V core with typical 255K-LE utilization (~80%), core current can reach 2-3 A and I/O current can reach several amps depending on switching activity, resulting in total package dissipation of 4-8 W. The F1152 FBGA package thermal resistance (theta_JA) is approximately 8 C/W with a properly designed thermal via array and heatsink; without thermal management, junction temperature can exceed 100C in still air. A 4-layer board with continuous inner-plane thermal vias under the BGA is recommended.

The 1152-ball F1152 BGA uses 1.0 mm ball pitch, requiring laser-drilled microvias or sequential lamination PCB fabrication. Escape routing must be planned in the Quartus II pin planner before PCB layout to avoid neck-downs. For high-speed differential pairs, use length-matched (within 5 mil) 100 ohm differential impedance with 4-layer stack-up. BGA break-out should use dog-bone fan-out on the top layer with via-in-pad for inner rows if the board budget allows.

Do not leave the MSEL[3:0] configuration mode pins floating - they select the configuration scheme (AS, AP, PS, FPP, JTAG) and must be tied high or low per the chosen mode. The CONF_DONE and nSTATUS pins require external 10 kohm pull-up resistors to VCCPD. JTAG pins TCK, TMS, TDI require pull-ups to VCCPD; TDO floats. Failing to observe these pin-connection rules is the most common cause of configuration failures in Stratix III boards.

Informações de conformidade

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

Sem chumbo

Yes

Sem halogênios

Unknown

Minerais de conflito

Compliant

RoHS compliant per Altera/Intel product ordering information. The C3NES suffix indicates lead-free / RoHS-compliant factory original packaging. AEC-Q100 is not applicable as this is a programmable logic device, not an automotive-grade IC. Halogen-free status not explicitly confirmed in available data - mark unknown.

Dados verificados em: 2026-09-09 — dados verificados e curados pela equipe de engenharia de componentes da XAIPART

Fontes: Distributor, Distributor, Distributor, Distributor, Distributor, Distributor, Distributor, Manufacturer Datasheet, Distributor, Distributor

Buscas relacionadas

EP3SE260F1152C3NES EP3SE260F1152C3NES datasheet Altera EP3SE260F1152C3NES Stratix III E 255K LE FPGA 1152-ball FBGA FPGA 744 I/O EP3SE260F1152C3NES for ASIC prototyping EP3SE260F1152C3NES vs EP3SE110F1152C3 EP3SE260F1152C3NES drop-in replacement buy EP3SE260F1152C3NES online what is the maximum Fmax of EP3SE260F1152C3NES EP3SE260F1152C3NES last time buy high-density 65nm FPGA 1.1V core

Componentes & termos relacionados

Altera Intel FPGA EP3SE260F1152C3NES EP3SE260F1152C3N EP3SE260F1152C3 EP3SE260F1152C2N EP3SE260F1152C2G EP3SE260F1152C2 EP3SE110F1152C3 Stratix III E Stratix III Enhanced FPGA Field Programmable Gate Array Programmable Logic Device PLD FBGA FineLine BGA 1152-ball BGA 1.0 mm ball pitch 65 nm process 1.1 V core 255,000 logic elements 744 user I/Os 16,672,768 bits embedded memory 768 18x18 multipliers 12 PLLs Hard PCIe Gen1/Gen2 DDR3 memory controller Quartus II AEC-Q100 RoHS REACH ASIC prototyping Software-defined radio Video processing Radar signal processing