Altera

EPM5192AQC100-20 - 192-Macrocell MAX 5000 EPLD, 33ns | Altera

N.º da peça: EPM5192AQC100-20 ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

5 V (typical, MAX 5000 family) Vdss 100-lead PQFP (R-PQFP-G100) Package 66.7 MHz Speed

A partir de $11.85 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-12

Preços por volume

Qtd.	Preço unitário	Total
1	$18.5	$18,50
10	$16.2	$162,00
100	$14.5	$1.450,00
500	$13.1	$6.550,00
1.000	$11.85	$11.850,00

ℹ️ Todos os preços estão em USD

Ver datasheet (PDF) Ver alternativas

Quantidade

EPM5192AQC100-20 Visão geral

The Altera EPM5192AQC100-20 is a high-density, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, integrating 192 macrocells with a maximum clock frequency of 66.7 MHz and a pin-to-pin propagation delay of 33 ns in a 100-lead PQFP package (R-PQFP-G100).

A Complex PLD (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays on a single CMOS die, providing deterministic combinatorial and registered logic with predictable timing. Within the broader hierarchy, the EPM5192AQC100-20 belongs to: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. The MAX 5000 family sits between classic 22V10-style SPLDs and modern high-density FPGAs, offering deterministic timing, instant-on operation, and high drive strength suitable for bus interface glue logic and address decoding.

Key features include 192 macrocells (organized into logic array blocks), 33 ns propagation delay, a 0.65 mm terminal pitch PQFP-100 footprint, and CMOS process technology with UV-erasable or one-time-programmable configuration memory. The device supports 5V operation (typical for the MAX 5000 family) and is housed in a 100-lead plastic quad flat pack (PQFP) rated for the commercial temperature range. Its high-drive I/O cells are well suited for TTL and CMOS bus interfacing.

The EPM5192AQC100-20 uses a classic EE-CMOS/UV-CMOS programmable interconnect architecture with a global interconnect matrix, ensuring uniform and predictable timing across all macrocells. Designers rely on this deterministic delay for asynchronous logic decoding where race conditions cannot be tolerated, and the 33 ns worst-case propagation delay is comparable to bipolar PAL devices while consuming far less power.

Typical applications include address decoding for microprocessor and DSP systems, bus interfacing and arbitration logic, state-machine controllers, and legacy industrial glue-logic replacement. The 192-macrocell capacity is well matched to wide-word decoders (e.g., 24-bit or 32-bit address decoding) and multi-channel peripheral control.

When designing with this device, treat the PQFP-100 as a through-hole or socketed assembly footprint: the 0.65 mm pitch demands careful PCB layout and the package is generally not hand-solderable. Because the part is in the MAX 5000 family (an older technology node), confirm long-term availability and consider newer MAX II/MAX V CPLDs for new designs unless pin-compatibility to the legacy footprint is mandatory.

This page synthesizes distributor pricing, drop-in same-family variants, and practical design notes for legacy support use cases not covered in the original 1990s-vintage datasheet.

Alternativas drop-in para EPM5192AQC100-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM5192AQC100-20 (mesmo formato e footprint) — diferindo em Package, Device Type, Propagation Delay (tPD), Technology, Mounting Type.

EPM5192AGC-15

Altera

Package: Ceramic Pin Grid Array (PGA)

Propagation Delay (tPD): 15 ns (pin-to-pin, -15 speed grade)

Technology: CMOS, UV-erasable EPROM