KSZ9893RNXC-TR - 3-Port Gigabit Ethernet Switch, 64-VQFN | Microchip
N.º da peça: KSZ9893RNXC-TR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $13.67 | $13,67 |
| 10 | $12.3 | $123,00 |
| 100 | $10.85 | $1.085,00 |
| 500 | $9.55 | $4.775,00 |
| 1.000 | $8.65 | $8.650,00 |
KSZ9893RNXC-TR Visão geral
A managed Ethernet switch is a layer-2 networking IC responsible for connecting end devices on the same local area network. Within the broader taxonomy, microchip ISZ9893RNXC-TR falls under Ethernet switch IC -> network interface controller -> communication IC -> semiconductor. These switches typically sit on the same PCB as a host processor (via SPI/I2C/MII/RGMII), handling MAC-layer frame forwarding, address learning, queueing, and traffic classification while offloading these tasks from the application CPU.
Key features include support for Energy Efficient Ethernet (EEE), Wake-on-LAN (WOL), Quality of Service (QoS), LinkMD cable diagnostics, and MIB counters for network telemetry. The KSZ9893RNXC-TR is configured via SPI or I2C management interfaces and supports IEEE 802.1Q VLAN, 802.1p priority, and 802.3x flow control. Two of the three ports are full PHY transceivers with HP Auto-MDI/MDIX, while the third port exposes RGMII/MII/RMII to an external MAC or SoC.
Architecturally, the KSZ9893R family uses a 1.2 GHz SerDes core for the integrated PHYs, with on-chip termination and adaptive equalization for 1000BASE-T operation over CAT5e cable. The store-and-forward fabric supports 12K-entry address lookup and 4 priority queues per output port. Per-port egress shapers and rate limiting use leaky-bucket algorithms, and the device integrates PTP hardware timestamping for IEEE 1588 applications when configured with external 25 MHz reference.
Typical applications include standalone 10/100/1000 Mbps Ethernet switches, VoIP infrastructure switches, Wi-Fi access-point gateways, industrial control switches, broadband gateways, networked measurement and control systems, and security/surveillance systems. The integrated PHY count reduces external magnetics and RJ-45 count, simplifying the BOM for 2+1 + fan managed Gigabit designs.
Designers should ensure the 25 MHz reference clock source is within ±50 ppm to meet 1000BASE-T jitter requirements, and follow Microchip reference schematics for the central-tap magnetics and 49.9 ohm termination. The device requires 1.2 V and 3.3 V supplies; both rails should be decoupled with 10 uF + 0.1 uF capacitors near the package.
This page synthesizes distributor pricing for the KSZ9893RNXC-TR, drop-in package-compatible variants, and practical design notes not aggregated on any single distributor page, giving engineers a one-stop reference for selecting and laying out this Ethernet switch IC.
Alternativas drop-in para KSZ9893RNXC-TR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com KSZ9893RNXC-TR (mesmo formato e footprint) — diferindo em Package, Operating Temperature, MAC Interface, MSL Level, Number of Ports.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
KSZ9893RNXU
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
KSZ9893RNXC
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
KSZ9031RNXIC-TR
✅ Drop-In✓ Em estoque
$4.3 / unidade
Ver ficha técnica →KSZ9031RNXIA
✅ Drop-In✓ Em estoque
$3.27 / unidade
Ver ficha técnica →KSZ9893RNXC-TR Especificações (publicadas pelo fabricante)
| Product Type | 3-Port Gigabit Ethernet Switch with RGMII/MII/RMII |
| Number of Ports | 3 (2 integrated PHY + 1 MAC interface) |
| PHY Speed | 10/100/1000 Mbps |
| Standards Compliance | IEEE 802.3, IEEE 802.3u, IEEE 802.3ab, IEEE 802.3az (EEE), IEEE 802.1Q, IEEE 802.1p |
| External MAC Port Interface | RGMII / MII / RMII (configurable) |
| Management Interface | I2C, SPI, MIIM (MDC/MDIO) |
| Integrated PHY Transceivers | 2x 10/100/1000 Base-TX with HP Auto-MDI/MDIX |
| Switch Architecture | Non-blocking store-and-forward |
| QoS Queues | 4 priority queues per egress port |
| Recursos | EEE, WOL, QoS, LinkMD, MIB counters, PTP hardware timestamping |
| Encapsulamento | 64-VQFN (8x8 mm), 0.4 mm pitch |
| Temperatura de operação | -40 C to +85 C (industrial) |
| Tensão de alimentação | 3.3 V (I/O) + 1.2 V (core) |
| Tipo de montagem | Surface Mount |
| Nível MSL | 3 (per JEDEC J-STD-020) |
| Status RoHS | Compliant |
| Lead-Free | Yes |
Configuração de pinos do KSZ9893RNXC-TR
| Pino 1 | VDDIO — 3.3V I/O supply |
| Pino 2 | GND — Ground |
| Pino 3 | TX1P — Port 1 PHY differential transmit positive |
| Pino 4 | TX1N — Port 1 PHY differential transmit negative |
| Pino 5 | RX1P — Port 1 PHY differential receive positive |
| Pino 6 | RX1N — Port 1 PHY differential receive negative |
| Pino 7 | VDD33A — 3.3V analog supply |
| Pino 8 | VDD12A — 1.2V analog supply |
| Pino 9 | TX2P — Port 2 PHY differential transmit positive |
| Pino 10 | TX2N — Port 2 PHY differential transmit negative |
| Pino 11 | RX2P — Port 2 PHY differential receive positive |
| Pino 12 | RX2N — Port 2 PHY differential receive negative |
| Pino 13 | GND — Ground |
| Pino 14 | VDD12 — 1.2V core supply |
| Pino 15 | VDDIO — 3.3V I/O supply |
| Pino 16 | NC — Not connected (per datasheet) |
| Pino 17 | REF_CLK — 25 MHz reference clock input |
| Pino 18 | GND — Ground |
| Pino 19 | RESET_N — Active-low hardware reset |
| Pino 20 | INT_N — Active-low interrupt output |
| Pino 21 | MDC — MIIM management clock |
| Pino 22 | MDIO — MIIM management data I/O |
| Pino 23 | SDA — I2C data (config interface) |
| Pino 24 | SCL — I2C clock (config interface) |
| Pino 25 | SPI_SCS — SPI chip select (config interface) |
| Pino 26 | SPI_CLK — SPI clock (config interface) |
| Pino 27 | SPI_MOSI — SPI master-out slave-in |
| Pino 28 | SPI_MISO — SPI master-in slave-out |
| Pino 29 | GND — Ground |
| Pino 30 | VDDIO — 3.3V I/O supply |
| Pino 31 | RGMII_TXC — Port 3 RGMII transmit clock |
| Pino 32 | RGMII_TXD3 — Port 3 RGMII transmit data 3 |
| Pino 33 | RGMII_TXD2 — Port 3 RGMII transmit data 2 |
| Pino 34 | RGMII_TXD1 — Port 3 RGMII transmit data 1 |
| Pino 35 | RGMII_TXD0 — Port 3 RGMII transmit data 0 |
| Pino 36 | RGMII_TXCTL — Port 3 RGMII transmit control |
| Pino 37 | RGMII_RXC — Port 3 RGMII receive clock |
| Pino 38 | RGMII_RXD3 — Port 3 RGMII receive data 3 |
| Pino 39 | RGMII_RXD2 — Port 3 RGMII receive data 2 |
| Pino 40 | RGMII_RXD1 — Port 3 RGMII receive data 1 |
| Pino 41 | RGMII_RXD0 — Port 3 RGMII receive data 0 |
| Pino 42 | RGMII_RXCTL — Port 3 RGMII receive control |
| Pino 43 | GND — Ground |
| Pino 44 | VDD12 — 1.2V core supply |
| Pino 45 | NC — Not connected (per datasheet) |
| Pino 46 | LED1_0 — Port 1 LED0 indicator |
| Pino 47 | LED1_1 — Port 1 LED1 indicator |
| Pino 48 | LED2_0 — Port 2 LED0 indicator |
| Pino 49 | LED2_1 — Port 2 LED1 indicator |
| Pino 50 | LED3_0 — Port 3 LED0 indicator |
| Pino 51 | LED3_1 — Port 3 LED1 indicator |
| Pino 52 | GND — Ground |
| Pino 53 | NC — Not connected (per datasheet) |
| Pino 54 | NC — Not connected (per datasheet) |
| Pino 55 | NC — Not connected (per datasheet) |
| Pino 56 | GND — Ground |
| Pino 57 | VDDIO — 3.3V I/O supply |
| Pino 58 | VDD12 — 1.2V core supply |
| Pino 59 | GND — Ground |
| Pino 60 | GND — Ground |
| Pino 61 | GND — Ground |
| Pino 62 | GND — Ground (thermal slug pad) |
| Pino 63 | GND — Ground (thermal slug pad) |
| Pino 64 | GND — Ground (thermal slug pad) |
Características de potência e térmicas
| Temperatura de Funcionamento | -40 C to +85 C (industrial) |
| Entrada de Potência | 3.3 V (I/O) + 1.2 V (core) |
Parâmetros de entrada de potência e térmicos para KSZ9893RNXC-TR, conforme publicados pelo fabricante.
Aplicações típicas
KSZ9893RNXC-TR é adequado para 6 aplicaçãos: Industrial Ethernet Switch, Wi-Fi Access Point Gateway, Broadband Gateway / Router, VoIP Infrastructure Switch, Networked Measurement and Control System, Security / Surveillance System.
Industrial Ethernet Switch
The KSZ9893RNXC-TR is purpose-built for compact industrial Ethernet switches requiring managed layer-2 switching with QoS and VLAN. Its integrated dual Gigabit PHYs eliminate external transceiver BOM, and the 64-VQFN (8x8 mm) package fits within DIN-rail and panel-mount switch housings. The device supports IEEE 1588 PTP hardware timestamping for sub-microsecond synchronization required by industrial automation protocols like PROFINET and EtherNet/IP, and its -40C to +85C industrial temperature grade handles factory floor environments. LinkMD cable diagnostics enable remote fault detection across plant floors.
Recomendado
Wi-Fi Access Point Gateway
Wi-Fi access points with wired LAN ports benefit from the KSZ9893RNXC-TR's three-port configuration - typically two LAN ports plus the RGMII link to the wireless SoC. The device's EEE (Energy Efficient Ethernet) reduces idle-port power consumption by up to 70% during low-traffic periods, extending battery life in PoE-powered APs. QoS prioritization ensures voice and video traffic receive priority queueing with low latency. The integrated HP Auto-MDI/MDIX eliminates crossover cable requirements during field installation.
Recomendado
Broadband Gateway / Router
The KSZ9893RNXC-TR suits broadband CPE gateways that need a managed switch fabric between WAN, LAN, and IP phone STB-side Ethernet connections. Support for IEEE 802.1Q VLAN tagging enables service-provider triple-play deployments, while 802.1p QoS prioritization reserves bandwidth for latency-sensitive voice traffic. The third configurable RGMII/MII/RMII port can connect to the host processor's MAC for WAN routing, while two PHY ports serve LAN endpoints. Wake-on-LAN enables remote device management.
Recomendado
VoIP Infrastructure Switch
VoIP infrastructure switches require reliable QoS to prioritize voice traffic over data. The KSZ9893RNXC-TR's four priority queues per egress port and 802.1p priority tagging deliver deterministic voice QoS with sub-millisecond latency variation. The integrated dual PHYs provide direct connection to two VoIP phones or downstream switches, while the third RGMII port connects to a host processor for PBX-Configuration call control. VLAN tagging isolates voice and data traffic across shared infrastructure.
Recomendado
Networked Measurement and Control System
Industrial measurement and control systems with distributed Ethernet sensors use the KSZ9893RNXC-TR for deterministic Ethernet connectivity. The device's PTP hardware timestamping (IEEE 1588) enables synchronized data acquisition across distributed measurement nodes. The integrated LinkMD cable diagnostics identify open and short cable faults for predictive maintenance, and the industrial temperature range handles outdoor and factory floor conditions. The compact 64-VQFN package fits within space-constrained sensor housings.
Recomendado
Security / Surveillance System
IP security camera systems with multiple PoE ports benefit from the KSZ9893RNXC-TR's three-port managed switch with QoS. Video traffic from IP cameras can be tagged for guaranteed bandwidth allocation, ensuring smooth streaming even under network congestion. The RGMII/MII/RMII third port connects to the host NVR processor, while two PHY ports serve camera uplinks. Wake-on-LAN enables power-saving mode for cameras during off-hours, and VLAN tagging isolates security traffic on shared corporate networks.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para KSZ9893RNXC-TR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | KSZ9893RNXU | KSZ9893RNXC | KSZ9031RNXIC-TR | KSZ9031RNXIA |
|---|---|---|---|---|---|
| Package | 64-VQFN (8x8 mm) | 64-VQFN (8x8 mm) | 64-VQFN (8x8 mm) | 64-QFN (8x8 mm) family | 64-QFN |
| Brand | Microchip | Microchip | Microchip | Microchip | Microchip |
| Function | 3-Port Gigabit Switch | 3-Port Gigabit Switch | 3-Port Gigabit Switch | Single-Port Gigabit PHY | Single-Port Gigabit PHY |
| Integrated PHY Ports | 2 | 2 | 2 | 1 | 1 |
| MAC Interface | RGMII/MII/RMII | RGMII/MII/RMII | RGMII/MII/RMII | RGMII only | RGMII only |
| Operating Temperature | -40C to +85C | -40C to +105C | -40C to +85C | -40C to +85C | -40C to +85C |
| EEE Support | — | Yes | Yes | Yes | Yes |
| Qty-1 Price (USD, Oct 2026) | $13.67 | ~$14.50 | ~$13.00 | ~$5.00 | ~$5.50 |
| Pin-to-Pin Compatible | Reference | Yes (drop-in) | Yes (drop-in) | No (different function) | No (different function) |
Principais diferenciais
- 3-port managed Gigabit Ethernet switch in a single 64-VQFN IC (vs KSZ9031RNXIC-TR (single-port PHY))
- Industrial temperature grade with PTP hardware timestamping (vs KSZ8863RLLI-TR (3-port Fast Ethernet))
- Single-IC managed layer-2 switch with QoS and VLAN (vs KSZ8995MAI (5-port 10/100 Mbps unmanaged))
Notas de projeto
Route the two Gigabit PHY differential pairs (TX1P/N, RX1P/N, TX2P/N, RX2P/N) as 100-ohm differential traces with maximum length matching of 0.13 mm (5 mil) within each pair. Place the 49.9-ohm 1% termination resistors within 4 mm of the KSZ9893RNXC-TR pins. Use ground-reference shielding (copper pour with ground stitching vias every 5 mm) beneath the differential traces to maintain 100-ohm impedance and minimize crosstalk to adjacent signals. Keep the trace length from the PHY outputs to the magnetics centerless than 25 mm for 1000BASE-T compliance.
The KSZ9893RNXC-TR requires two supply rails: 3.3 V (VDDIO/VDD33A) for I/O and analog PHY, and 1.2 V (VDD12/VDD12A) for the digital core. Decouple each supply pin with a 0.1 uF X7R ceramic capacitor placed within 2 mm of the pin, plus a bulk 10 uF ceramic at each supply domain. Estimated combined power consumption is approximately 300 mW per active 1000BASE-T port and 50 mW per idle port in EEE mode. The 25 MHz reference clock supply should be from a low-jitter source with less than 50 ppm frequency accuracy.
Do not omit the central-tap connection on the Ethernet magnetics - both TX and RX center taps must connect to the analog 3.3 V rail through a separate bias network per Microchip reference design. Failing to connect center taps results in degraded 1000BASE-T link margin and LinkMD misreporting. Additionally, ensure the 25 MHz reference clock traces are short and shielded with ground vias on both sides to prevent EMI coupling into the PHY analog blocks. The RGMII/MII/RMII selection straps must be pulled to the correct logic level at RESET_N deassertion per the datasheet strap configuration table.
Informações de conformidade
RoHS compliant per Microchip product page. Not AEC-Q100 qualified - this part is for industrial/commercial use, not automotive. Halogen-free status not explicitly stated in the available web data.
