LAN91C111-NU - 10/100 Ethernet MAC/PHY | Microchip
N.º da peça: LAN91C111-NU ✓ AtivoLAN91C111-NU Visão geral
An Ethernet MAC and PHY are the two principal layers required for a conventional 10/100 Ethernet connection. The MAC organizes frames and manages access to the network, while the PHY converts digital data into signals suitable for twisted-pair cabling. Integrating both functions into one controller reduces external component count and simplifies embedded network designs compared with separate MAC and PHY implementations. The LAN91C111-NU belongs to the broader interface IC and Ethernet controller hierarchy.
Key features include 10/100 Mbps dual-speed operation, support for 8-bit, 16-bit, and 32-bit host bus configurations, and 8 KB of internal FIFO memory. The manufacturer describes the LAN91C111 as implementing the MAC and PHY portions of CSMA/CD and using a parallel host interface suited to embedded processors. Its mixed-signal construction places network termination and transceiver functions alongside the digital controller logic.
The configurable host interface allows a design to balance throughput, wiring, and memory efficiency. An 8-bit bus can reduce the number of processor connections, while a 32-bit bus can transfer data more efficiently when the host bus and system timing support it. The internal transmit and receive FIFOs help decouple host access from network timing, although firmware, interrupt handling, and buffer configuration remain essential parts of a reliable driver design.
Typical applications include embedded industrial controllers, print servers, set-top boxes, embedded Linux systems, instrument-control equipment, and compact network appliances. The integrated 10/100 Ethernet interface is useful when a system needs a deterministic parallel host connection rather than a serial network interface. It can also support legacy Fast Ethernet equipment where both 10 Mbps and 100 Mbps operation are required.
Layout is the primary design consideration. Place the Ethernet magnetics, line-side protection, and PHY-related components close to the network connector, while keeping the parallel host bus away from sensitive analog network traces. Confirm power, clock, reset, transceiver, and host-interface requirements against the manufacturer datasheet before releasing the PCB layout. The package library does not contain a dedicated 128-lead TQFP drawing, so use the manufacturer pin-description table for assignments.
This page combines the LAN91C111-NU device function, verified family variants, cross-reference findings, application guidance, and practical integration considerations. It also distinguishes true same-package options from unrelated Ethernet controllers that may require different hosts, PHYs, packages, or driver changes.
Alternativas drop-in para LAN91C111-NU — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LAN91C111-NU (mesmo formato e footprint) — diferindo em Device Type, Package.
LAN91C111I-NU
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LAN91C111-NU-E2
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LAN91C111-NE
✅ Drop-In ⚠️ Especificações não verificadasConsulte o preço
Ver ficha técnica →LAN91C111I-NE
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
LAN91C111
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
LAN91C111-NU Especificações
| Device Type | 10/100 non-PCI Ethernet single-chip MAC and PHY |
| Supported Data Rates | 10 Mbps and 100 Mbps |
| Host Interface | 8-bit, 16-bit, or 32-bit parallel bus |
| Internal FIFO Memory | 8 KB dynamically configurable TX/RX SRAM |
| Network Standard | 10/100 Base-T/TX |
| Protocol Support | CSMA/CD |
| Tensão de alimentação | 3.3 V |
| Encapsulamento | 128-lead TQFP, 14 mm x 14 mm |
| Tipo de montagem | Surface mount |
| Architecture | Mixed-signal analog and digital |
| Automatic Negotiation | Supported |
Guia de Configuração de Pinos do LAN91C111-NU 128-lead tqfp, 14 mm x 14 mm
Configuração de pinos para LAN91C111-NU (pacote 128-lead tqfp, 14 mm x 14 mm). A numeração dos pinos, funções e diagramas de conexão estão definidos no datasheet do fabricante. Consulte-o para o footprint exato e diretrizes de soldagem.
Nenhum dado detalhado de pinagem disponível para LAN91C111-NU.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
LAN91C111-NU é adequado para 6 aplicaçãos: Embedded Industrial Controller, Networked Print Server, Embedded Linux Gateway, Test and Measurement Instrument, Set-Top and Media Appliance, Networked Sensor and IoT Controller.
Embedded Industrial Controller
The LAN91C111-NU fits an embedded industrial controller that requires a direct parallel connection to its processor instead of an external serial Ethernet interface. Its integrated 10/100 Mbps MAC and PHY reduces the number of network components, while the selectable 8-bit, 16-bit, and 32-bit host bus allows the PCB architect to match processor I/O width and timing. The 8 KB dynamically configurable TX/RX FIFO helps buffer traffic between network events and host servicing. Place the magnetics and protection near the connector, isolate line-side routing from digital signals, and follow Microchip application note en562794 for the supported interface configuration.
Recomendado
Networked Print Server
The LAN91C111-NU can provide the Fast Ethernet connection used by a compact print server when its host supports the controller's 8-bit, 16-bit, or 32-bit parallel bus. The integrated MAC/P PHY handles both 10 Mbps and 100 Mbps links, and the internal 8 KB FIFO allows the controller to buffer frames during host printing and protocol processing. A 16-bit or 32-bit host bus can reduce transfer overhead when the processor and memory system support parallel transfers. The implementation still requires a correct network-driver interface, interrupt handling, and a segregated analog Ethernet section around the connector and magnetics.
Recomendado
Embedded Linux Gateway
The LAN91C111-NU is suitable for an embedded Linux gateway whose bus architecture can accommodate a parallel Ethernet controller. The device supports 10 Mbps and 100 Mbps links, auto-negotiation, configurable host-bus width, and an 8 KB dynamically configurable transmit and receive FIFO. These features allow a driver to use the narrower interface where pin count is constrained or the wider interface where packet throughput is the priority. Firmware must coordinate interrupts, descriptor or buffer management, and the network stack. Board layout should follow the manufacturer's separated analog and digital arrangement to avoid coupling Ethernet line-side energy into the host bus.
Recomendado
Test and Measurement Instrument
The LAN91C111-NU can serve as the Ethernet communication interface in compact test and measurement equipment requiring 10/100 Mbps connectivity. Its selectable parallel host interface permits integration with an embedded controller or instrumentation processor, and the integrated PHY avoids a separate Ethernet transceiver. The 8 KB FIFO provides useful separation between network reception and slower host-side processing, which is important when transferring measurement data or receiving remote commands. Use the manufacturer's pin and layout guidance, protect the network connector with the recommended arrangement, and verify driver timing against the instrument's processor performance.
Recomendado
Set-Top and Media Appliance
The LAN91C111-NU is appropriate for a set-top box or media appliance that needs a simple Fast Ethernet host connection. The 10/100 Mbps support covers legacy and standard Fast Ethernet networks, while the 8/16/32-bit host-bus options let the designer balance processor pin usage against transfer efficiency. Its integrated MAC/PHY and configurable FIFO reduce external hardware and software buffering requirements. A successful design still needs stable firmware drivers, interrupt prioritization for streaming traffic, and careful separation of the Ethernet analog section from sensitive audio or video circuitry. Confirm operating-temperature limits for the selected ordering suffix against the appliance enclosure environment.
Recomendado
Networked Sensor and IoT Controller
The LAN91C111-NU can add wired Fast Ethernet connectivity to an IoT controller or industrial sensor node that has a compatible parallel host processor. The device operates at 10 Mbps or 100 Mbps and includes an 8 KB configurable FIFO for separating network traffic from application processing. An 8-bit host configuration can conserve processor pins, whereas a 16-bit or 32-bit configuration can improve packet-transfer efficiency. The design should use the recommended Ethernet magnetics and protection, maintain a controlled analog network layout, and include firmware support for link negotiation, interrupt servicing, and continuous data transfer. The selected suffix must satisfy the deployment temperature range.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LAN91C111-NU — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LAN91C111I-NU | LAN91C111-NU-E2 | LAN91C111-NE | LAN91C111I-NE | LAN91C111 |
|---|---|---|---|---|---|---|
| Manufacturer | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 128-lead TQFP, 14 mm x 14 mm | 128-lead TQFP, 14 mm x 14 mm | 128-lead TQFP, 14 mm x 14 mm | 128-lead TQFP, 14 mm x 14 mm | 128-lead TQFP, 14 mm x 14 mm | 128-lead TQFP, 14 mm x 14 mm |
| Device Function | 10/100 non-PCI Ethernet single-chip MAC and PHY | 10/100 non-PCI Ethernet single-chip MAC and PHY | 10/100 non-PCI Ethernet single-chip MAC and PHY | 10/100 non-PCI Ethernet single-chip MAC and PHY | 10/100 non-PCI Ethernet single-chip MAC and PHY | 10/100 non-PCI Ethernet single-chip MAC and PHY |
| Supported Data Rates | 10 Mbps and 100 Mbps | 10 Mbps and 100 Mbps | 10 Mbps and 100 Mbps | 10 Mbps and 100 Mbps | 10 Mbps and 100 Mbps | 10 Mbps and 100 Mbps |
| Host Interface Width | 8-bit, 16-bit, or 32-bit parallel bus | 8-bit, 16-bit, or 32-bit parallel bus | 8-bit, 16-bit, or 32-bit parallel bus | 8-bit, 16-bit, or 32-bit parallel bus | 8-bit, 16-bit, or 32-bit parallel bus | 8-bit, 16-bit, or 32-bit parallel bus |
| Internal FIFO Memory | 8 KB dynamically configurable TX/RX SRAM | 8 KB dynamically configurable TX/RX SRAM | 8 KB dynamically configurable TX/RX SRAM | 8 KB dynamically configurable TX/RX SRAM | 8 KB dynamically configurable TX/RX SRAM | 8 KB dynamically configurable TX/RX SRAM |
| Automatic Negotiation | Supported | Supported | Supported | Supported | Supported | Supported |
Principais diferenciais
- Integrated Fast Ethernet MAC and PHY (vs LAN91C111I-NU)
- Flexible parallel host connectivity (vs LAN91C111-NU-E2)
- Integrated frame buffering (vs LAN91C111-NE)
- Automatic link negotiation (vs LAN91C111I-NE)
Notas de projeto
Follow the Ethernet reference layout in Microchip application note en562794. Place the controller's line-side network section close to the RJ45 connector and magnetics, keep the TX and RX differential pairs short and controlled-impedance, and route them away from clocks and the parallel host bus. Confirm component placement against the manufacturer's recommended network termination and protection arrangement before fabrication.
Treat the analog and digital portions as separate layout regions even though both functions are integrated in one package. Provide the specified analog and digital supply connections and place their bypassing capacitors at the associated pins. Keep the 8/16/32-bit host bus away from the Ethernet transformer and connector area, and use the manufacturer pin-description table to assign every one of the 128 package leads.
Do not substitute the device solely because another Ethernet controller also supports 10/100 Mbps. The replacement must have the same 128-lead footprint, compatible host-bus width, power connections, clocking method, interrupt behavior, and register expectations. For LAN91C111I-NU, also verify the manufacturer-defined temperature range and the I suffix qualification requirements before releasing a substitution.
Separate analog and digital supply distribution where the manufacturer datasheet permits or requires it, and decouple each domain close to the package pins. Check the exact absolute maximum and operating voltage limits from the manufacturer datasheet because only the nominal 3.3 V supply is identified here. Validate startup sequencing, clock stability, and reset behavior in hardware before relying on link negotiation.
Informações de conformidade
No product-specific compliance declarations were identified for the exact LAN91C111-NU ordering code.
