PS8926 - 16Gbps PCIe Gen 4 16-Lane Retimer | Parade Technologies
N.º da peça: PS8926 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $78.5 | $78,50 |
| 10 | $74.2 | $742,00 |
| 100 | $68.9 | $6.890,00 |
| 500 | $62.4 | $31.200,00 |
| 1.000 | $55.8 | $55.800,00 |
PS8926 Visão geral
A PCIe retimer is a signal-conditioning device that sits between a PCIe root complex or endpoint and a connector or cable, rebuilding the eye diagram of a degraded high-speed serial link to extend the reach of a PCIe channel beyond what passive copper allows. Retimers belong to the broader class of high-speed serial link redrivers and signal conditioners within the mixed-signal interface IC category, alongside redrivers, crosspoint switches, and packet switches. The PS8926 specifically implements the retimer (not redriver) function, which means it includes its own PLL/clock-data recovery (CDR) per lane and is transparent to PCIe link training and LTSSM state machine, passing modified TS1/TS2 ordered sets between the two link partners.
Key features include PCIe 4.0 spec compliance with backward compatibility to Gen 1 (2.5 Gbps), Gen 2 (5 Gbps), and Gen 3 (8 Gbps), a low-latency architecture for cut-through applications, Intel SRIS/SRNS support implied by the supplemental-features compliance citation, and adaptive CTLE + DFE equalization that compensates for channel loss up to typical PCIe 4.0 reach budgets. Each of the 16 bidirectional lanes independently performs transmit de-emphasis and receive equalization, and the device is managed over I2C/SMBus for per-lane tuning, eye-margin monitoring, and firmware updates.
Typical applications include workstation motherboards, enterprise data center servers, NVMe storage backplanes, accelerator/GPU add-in cards that require long PCB traces or PCIe cables between the host and the endpoint, and riser-card assemblies. It is intended for high-lane-count PCIe bus widths where passive redrivers cannot recover the Gen 4 eye and a true retimer is required by system firmware.
When designing with this device, follow Intel's standard BGA footprint layout exactly to share mechanical design across compliant retimers, provide adequate thermal dissipation for the BGA-354 package, and budget PCIe link-training margin using the device's diagnostic eye-margin features.
This page synthesizes distributor stock indicators, parametric alternatives within the same BGA footprint, and design notes for signal-integrity verification not found in the manufacturer product page.
Alternativas drop-in para PS8926 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com PS8926 (mesmo formato e footprint) — diferindo em Function, Maximum Data Rate, Package.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
PS8926A
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
PS8926BGA354GTR-A2
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
PS8926 Especificações
| Função | PCIe Gen 4 16-lane Retimer (32 differential channels) |
| PCIe Specification Compliance | PCI Express 4.0 (backward compatible to Gen 1/2/3) |
| Supported Data Rates | 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps |
| Maximum Data Rate | 16 Gbps (PCIe Gen 4) |
| Lanes | 16 bidirectional (32 differential channels) |
| Direction | Bidirectional |
| Latency | Low (cut-through capable) |
| Equalization | Adaptive CTLE + DFE per lane |
| Intel Compliance Document | PCI Express 4.0 Retimer Supplemental Features and Standard BGA Footprint (Revision 004, June 2018) |
| Encapsulamento | BGA-354 (GTR) |
| Tipo de montagem | Surface Mount (BGA) |
| Operating Mode | PCIe Retimer (with CDR per lane) |
| Primary Applications | Workstations, enterprise servers, storage, risers |
Guia de Configuração de Pinos do PS8926 bga-354 (gtr)
Configuração de pinos para PS8926 (pacote bga-354 (gtr)). A numeração dos pinos, funções e diagramas de conexão estão definidos no datasheet do fabricante. Consulte-o para o footprint exato e diretrizes de soldagem.
Nenhum dado detalhado de pinagem disponível para PS8926.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
PS8926 é adequado para 6 aplicaçãos: Enterprise Server PCIe Gen 4 Backplane, NVMe Storage Array Switched Fabric, Workstation Motherboard PCIe Riser, GPU/Accelerator Add-in Card Host Interface, PCIe Cable Extension for Distributed Systems, Rack-Scale Composable Infrastructure.
Enterprise Server PCIe Gen 4 Backplane
The PS8926's 16 bidirectional lanes and 16 Gbps data rate make it a strong fit for enterprise server backplanes where multiple root-complex PCIe ports fan out to NVMe drives, accelerators, and SAS controllers across long PCB traces. Adaptive CTLE and DFE equalizers on each lane compensate for the channel loss of a typical 8-12 inch server PCB route plus a high-density connector, rebuilding the PCIe Gen 4 eye at the far end. Placed between the CPU package and the high-density connector array, the PS8926 extends PCIe link reach beyond what passive routing allows without consuming retimer-specific PCIe link-training states that the platform firmware already expects. The BGA-354 footprint follows Intel's standardized retimer mechanical outline, allowing layout reuse across server SKUs.
Recomendado
NVMe Storage Array Switched Fabric
NVMe storage arrays that fan out a single PCIe Gen 4 x16 host port across many NVMe SSD endpoints rely on retimers to maintain signal integrity across long switch-board traces and high-density connectors. The PS8926's 16 lanes provide the headroom to drive a PCIe switch downstream of the retimer while sustaining 16 Gbps per lane, and the adaptive CTLE/DFE automatically tracks channel drift across temperature and aging. In this application, the PS8926 sits on the switch card between the upstream host connector and the downstream PCIe switch ASIC, restoring the Gen 4 eye so that x4 NVMe drives downstream meet PCIe 4.0 base-spec BER requirements.
Recomendado
Workstation Motherboard PCIe Riser
Workstation motherboards often route PCIe x16 slots through riser cards or long PCB traces to support dual-slot GPU configurations and full-length add-in cards. The PS8926's low-latency retimer architecture preserves the Gen 4 link-training flow while restoring signal integrity across a typical riser-card-plus-slot budget that pushes the limits of Gen 4 passive routing. Used at the riser connector interface, the PS8926 enables workstation OEMs to maintain PCIe 4.0 compliance on x16 mechanical slots that would otherwise fall back to Gen 3 due to channel loss. Each lane's adaptive equalization tunes independently to the slot's specific loss profile.
Recomendado
GPU/Accelerator Add-in Card Host Interface
AI accelerator and GPU add-in cards often need a retimer on the host-side interface when the card's edge-finger connector and the motherboard's slot combine to exceed Gen 4 passive-channel loss budgets. The PS8926's 16 lanes deliver the full x16 PCIe Gen 4 link between the host root complex and the accelerator's upstream port, with per-lane adaptive CTLE and DFE that compensate for connector crosstalk and PCB skew. Placed near the card's edge connector, it allows accelerator vendors to use longer-than-usual host-routing topologies while still meeting PCIe 4.0 base-spec eye masks at the host endpoint.
Recomendado
PCIe Cable Extension for Distributed Systems
PCIe Gen 4 cable extensions between racks or across chassis partitions introduce high-frequency loss and connector crosstalk that passive copper cannot equalize. The PS8926's retimer architecture (with per-lane clock-data recovery, not just amplification) is exactly the function PCIe-SIG specifies for cable adapters and backplanes, rebuilding the eye at each cable segment. Used at both ends of a PCIe Gen 4 cable assembly, the PS8926 allows systems to push 16 Gbps across several meters of copper cable while preserving the LTSSM transparency that host firmware expects, enabling distributed accelerator and storage topologies.
Recomendado
Rack-Scale Composable Infrastructure
Composable infrastructure disaggregates compute, storage, and accelerators into pooled resources connected over PCIe Gen 4 fabric, often through retimer-dense switch trays. The PS8926's 16-lane count and Intel-standard BGA footprint allow switch tray designers to populate multiple retimers per tray using a shared PCB layout, dramatically simplifying the mechanical design. With low-latency cut-through operation, the PS8926 minimizes the added latency per retimer hop, keeping fabric-level latency budgets within the bounds expected by PCIe-SIG and composable-disaggregated software stacks.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para PS8926 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | PS8926A | PS8926BGA354GTR-A2 |
|---|---|---|---|
| Package | BGA-354 (GTR) | BGA-354 (GTR) - same Intel-standard retimer footprint | BGA-354 (GTR) - same Intel-standard retimer footprint |
| Brand | Parade Technologies | Parade Technologies | Parade Technologies |
| PCIe Generation | PCIe 4.0 | PCIe 4.0 | PCIe 4.0 |
| Maximum Data Rate | 16 Gbps | 16 Gbps | 16 Gbps |
| Lanes (Bidirectional) | 16 | 16 | 16 |
| Supported Speeds | 2.5 / 5 / 8 / 16 Gbps | 2.5 / 5 / 8 / 16 Gbps | 2.5 / 5 / 8 / 16 Gbps |
| Internal Temperature Sensor | No | Yes (added vs PS8926) | No (same die as PS8926) |
| Intel SRIS/SRIS Footprint Compliance | Yes (Intel Retimer doc Rev 004, June 2018) | Yes (same Intel-standard footprint) | Yes (same Intel-standard footprint) |
Principais diferenciais
- Intel-standardized retimer BGA footprint enables multi-vendor PCB layout reuse (vs Generic PCIe redrivers that use proprietary footprints)
- True retimer (with per-lane CDR) rather than redriver (amplifier-only) (vs Passive PCIe Gen 4 redrivers (e.g., repeater-only signal conditioners))
- 16 bidirectional lanes in a single device for high-lane-count links (vs Multiple x4 or x8 retimer devices cascaded to reach x16)
Notas de projeto
Place the PS8926 as close as practical to the high-density connector or cable receptacle to maximize the recovered-eye margin on the longest PCB trace segment. The BGA-354 footprint follows the Intel-standardized retimer mechanical outline (PCI Express 4.0 Retimer Supplemental Features and Standard BGA Footprint, Revision 004, June 2018), which pre-routes the high-speed differential pairs with 85-100 ohm differential impedance - verify with a 3D EM solver that the breakout region under the BGA matches the standard's via-field pattern.
Estimated: at full x16 Gen 4 traffic (16 Gbps x 16 lanes), a 16-lane retimer typically dissipates 4-6 W depending on equalization aggressiveness. With a BGA-354 thermal resistance of approximately 15-20 C/W (depends on PCB stack-up), the junction-to-ambient delta is roughly 80-100 C in still air, so a thermal via array under the BGA and at least 4-layer PCB with dedicated ground/power planes are recommended. The PS8926A variant integrates an internal temperature sensor that the host can read over I2C for closed-loop fan control.
Do not assume any retimer is pin-compatible with the PS8926 just because it advertises PCIe 4.0 support - the BGA ball-map differs between vendors. Only parts explicitly citing compliance with the Intel "PCI Express 4.0 Retimer Supplemental Features and Standard BGA Footprint" document (Revision 004, June 2018) share the same BGA-354 footprint. Confirm the ball-map from the manufacturer datasheet before substituting on an existing board design.
Informações de conformidade
RoHS, REACH, AEC-Q100, lead-free, halogen-free, and conflict-mineral status were not present in the verified web data; all set to 'unknown' pending manufacturer datasheet confirmation. The PS8926 is not an automotive-qualified part and is targeted at workstations, servers, and storage rather than AEC-Q100 applications.
