SI5365-C-GQ - 1.05GHz Pin-Programmable Clock Multiplier | Skyworks
N.º da peça: SI5365-C-GQ ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $46.15 | $46,15 |
| 10 | $41.54 | $415,40 |
| 100 | $37.38 | $3.738,00 |
| 500 | $33.64 | $16.820,00 |
| 1.000 | $30.28 | $30.280,00 |
SI5365-C-GQ Visão geral
A clock multiplier (also called a jitter-attenuating clock generator) is a timing IC in the broader clock generation and frequency synthesis hierarchy that takes a reference input and produces a clean, multiplied output clock. Jitter attenuators sit between a noisy reference source and a jitter-sensitive receiver, using a narrow-bandwidth phase-locked loop to remove accumulated jitter. The Si5365 belongs to the class of PLL-based clock multiplier ICs used in synchronous networking and high-speed serial systems.
Key features include any-frequency synthesis from 100 kHz to 1.05 GHz, a digitally programmable PLL loop bandwidth selectable from 150 kHz to 1.3 MHz via the BWSEL[1:0] pins, and pin-programmable frequency configuration that requires no host processor or EEPROM programming. The DSPLL architecture suppresses reference spurs and delivers low phase noise suitable for SONET/SDH-class jitter masks.
Technically, the device operates as a digital PLL with a high-resolution delta-sigma fractional-N feedback path, so output-to-input ratios can be any rational number within the operating ranges. Because the loop bandwidth is digitally set rather than set by RC components, jitter performance is repeatable from unit to unit and across temperature.
Typical applications include line-card and optical module clock distribution, SONET/SDH and OTN equipment timing, 10G Ethernet and Fibre Channel transceiver reference clocks, and jitter cleanup for recovered clocks from retiming circuits.
Design consideration: choose the BWSEL setting to balance jitter attenuation bandwidth against input tracking; a narrower bandwidth gives lower integrated jitter but less tolerance to reference wander.
This page synthesizes distributor pricing, drop-in alternative data, and practical design notes not found in the manufacturer datasheet.
Alternativas drop-in para SI5365-C-GQ — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SI5365-B-GQ
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
SI5365-A-GQ
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
SI5365-C-GQ Especificações
| Função | Pin-programmable precision clock multiplier / jitter attenuator |
| Technology | 3rd-generation DSPLL |
| Maximum Output Frequency | 1.05 GHz |
| Output Count | 1 |
| PLL Loop Bandwidth Range | 150 kHz to 1.3 MHz (BWSEL[1:0] pins) |
| Configuration Method | Pin-programmable (no EEPROM or host processor required) |
| External VCXO Required | No (integrated in DSPLL) |
| External Loop Filter Required | No |
| Encapsulamento | 100-TQFP (GQ) |
| Tipo de montagem | Surface Mount |
| Input Reference Type | Differential / single-ended clock input |
| Status RoHS | Compliant |
| Unit Price (Qty 1) | $46.15 (FPGACenter, as of 2026-10-10) |
| Datasheet Page Count | 27 pages |
Guia de Configuração de Pinos do SI5365-C-GQ 100-tqfp (gq)
Configuração de pinos para SI5365-C-GQ (pacote 100-tqfp (gq)). A numeração dos pinos, funções e diagramas de conexão estão definidos no datasheet do fabricante. Consulte-o para o footprint exato e diretrizes de soldagem.
Nenhum dado detalhado de pinagem disponível para SI5365-C-GQ.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
SI5365-C-GQ é adequado para 6 aplicaçãos: SONET/SDH Line Card Timing, Optical Module Clock Cleanup, 10G Ethernet and Fibre Channel Reference Clocks, Industrial Automation Timing Distribution, Test and Measurement Instrument Clocking, Broadcast and Professional Video Sync.
SONET/SDH Line Card Timing
The SI5365-C-GQ fits SONET/SDH line-card clocking because its DSPLL jitter attenuator can clean a recovered line clock to the strict jitter transfer and jitter generation masks these standards impose, with a programmable loop bandwidth from 150 kHz to 1.3 MHz. In a typical line card, a recovered clock from the optical module drives the reference input, and the Si5365 multiplies it to the system serializing clock, up to 1.05 GHz, with a single low-jitter output feeding the framer or SerDes. Because configuration is pin-strapped, no host I2C traffic is needed at boot, simplifying power sequencing. The absence of an external VCXO and loop filter reduces BOM count and eliminates analog tuning variance across production units.
Recomendado
Optical Module Clock Cleanup
In XFP/SFP+ optical transceiver applications, the SI5365-C-GQ attenuates jitter on a recovered clock before it is recirculated or used for retiming. The narrow-bandwidth DSPLL (as low as 150 kHz per the datasheet) suppresses reference jitter accumulated in the receive CDR, while any-frequency synthesis matches arbitrary line rates without a custom crystal. Designers strap BWSEL[1:0] to set the attenuation bandwidth appropriate to the wander budget of the module standard. Because the part integrates the VCO, the module layout stays compact around the 100-pin TQFP. The single-output architecture matches typical retiming use where one clean clock is sufficient, keeping power and cost below multi-output clock generator alternatives.
Recomendado
10G Ethernet and Fibre Channel Reference Clocks
The SI5365-C-GQ generates the low-jitter reference clock required by 10 Gigabit Ethernet and Fibre Channel SerDes, where excessive reference jitter directly erodes timing margin and bit-error performance. Any-frequency synthesis covers the standardized 156.25 MHz, 161.13 MHz, and derived reference rates as well as non-standard line rates, and the 1.05 GHz ceiling supports quarter-rate architectures. The DSPLL architecture converts a noisy backplane-recovered or motherboard clock into a clean source with jitter repeatable from unit to unit because bandwidth is digitally programmed instead of set by RC tolerance. Pin-programmability lets one PCB design serve multiple speed grades by changing straps rather than firmware, accelerating variant development across a product family.
Recomendado
Industrial Automation Timing Distribution
Industrial Ethernet and factory automation systems need deterministic, low-jitter clocks synchronized across nodes, and the SI5365-C-GQ addresses this by multiplying a recovered IEEE 1588-derived or backplane reference to the local PHY clock with strong jitter attenuation. Its pin-programmable configuration avoids firmware dependency, which suits long-lifecycle industrial equipment where software stacks change over decades of service. The 100-pin TQFP surface-mount package handles -based reflow assembly in standard industrial processes, and the DSPLL's digitally set loop bandwidth keeps jitter performance stable across the industrial temperature span. Because no external VCXO or loop filter is needed, the timing circuitry resists component-drift issues common in analog PLL designs deployed in harsh environments.
Recomendado
Test and Measurement Instrument Clocking
Bench and modular instruments require any-frequency clock synthesis for arbitrary sample-rate and trigger generation, and the SI5365-C-GQ's any-rational-ratio synthesis from a single reference, up to 1.05 GHz, matches this need without custom oscillators. The low phase noise of the 3rd-generation DSPLL keeps measurement noise floors intact, while the selectable 150 kHz to 1.3 MHz loop bandwidth lets instrument firmware trade jitter cleanup depth against reference tracking during frequency slews. Pin-strapped configuration enables hardware-selectable rate presets via relay or logic selection, useful for calibration modes. Since jitter performance is repeatable across production units, instrument manufacturers can guarantee specifications without per-unit PLL tuning, simplifying manufacturing test and calibration procedures across product lines.
Recomendado
Broadcast and Professional Video Sync
Broadcast facilities generate and clean reference clocks for SDI video, where the SI5365-C-GQ multiplies standard video references to serialization rates while attenuating genlock distribution jitter. Any-frequency synthesis covers the family of SD/HD/3G-SDI bit rates and their audio ancillary clocks from one reference, and the 1.05 GHz ceiling accommodates emerging higher-rate formats. The narrow DSPLL bandwidth rejects wander accumulated through long genlock cable runs, and jitter generation low enough for serial video masks is provided by the -C performance grade. Because no external VCXO is required, sync-generator cards remain compact, and the pin-programmable architecture allows hardware rate selection per card slot without management-controller involvement during startup.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SI5365-C-GQ — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SI5365-B-GQ | SI5365-A-GQ |
|---|---|---|---|
| Package | 100-TQFP (GQ) | 100-TQFP (GQ) - same | 100-TQFP (GQ) - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Max Output Frequency | 1.05 GHz | 1.05 GHz | 1.05 GHz |
| Configuration | Pin-programmable | Pin-programmable | Pin-programmable |
| Loop Bandwidth Range | 150 kHz to 1.3 MHz | 150 kHz to 1.3 MHz | 150 kHz to 1.3 MHz |
| Jitter Grade | -C (premium) | -B (standard) - looser jitter limits | -A (base) - loosest jitter limits |
| External VCXO Required | No | No | No |
Principais diferenciais
- Premium -C jitter grade in the same footprint (vs SI5365-B-GQ)
- Zero external analog tuning components (vs SI5365-A-GQ)
- Pin-only configuration (no firmware dependency) (vs SI5365-B-GQ)
Notas de projeto
Provide a solid, unbroken ground plane directly beneath the 100-pin TQFP and connect the package center thermal/ground pad to it with a via array (typically 3x3 or denser). Place 100 nF ceramic decoupling capacitors at every supply pin within 2 mm of the pin, plus bulk 10 uF per supply domain. Keep the reference input pair short and routed as a controlled-impedance differential pair. The Skyworks datasheet land pattern should be followed exactly for the GQ package to ensure solder joint reliability on the thermal pad.
BWSEL[1:0] selection trades jitter attenuation against reference tracking: choose 150 kHz-class bandwidths when cleaning a noisy recovered clock (maximum attenuation), and wider settings (toward 1.3 MHz) when the reference may wander or need fast lock. Route the 1.05 GHz-capable output as a 50-ohm single-ended or 100-ohm differential controlled-impedance trace with no stubs; series-terminate at the source if driving point-to-point CMOS loads. Verify the actual jitter generated at your specific output frequency against the -C grade limits in the datasheet, as jitter scales with output frequency.
Because the Si5365 is pin-programmable, frequency configuration is fixed at board build: an error in the frequency-selection strap resistors requires PCB rework, not just firmware change. Double-check the datasheet's frequency-selection pin tables against your reference and target frequencies before layout release. Also, do not substitute the -B or -A grade for the -C grade without re-verifying your system jitter budget, since grade differences are precisely in jitter limits. Finally, avoid sourcing from non-authorized brokers where counterfeit re-marked timing ICs are a known risk; buy from DigiKey, Mouser, or LCSC.
Informações de conformidade
RoHS compliance and lead-free status per distributor listings (LCSC, DigiKey). REACH, halogen-free, and conflict-minerals declarations not found in provided data - request part-specific compliance documents from Skyworks.
