SN74AUP1T34DCKR - 1-Bit Level Translator 0.9-3.6V SC-70-5 | TI
N.º da peça: SN74AUP1T34DCKR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $0.29 | $0,29 |
| 10 | $0.24 | $2,40 |
| 100 | $0.16 | $16,00 |
| 500 | $0.12 | $60,00 |
| 1.000 | $0.09 | $90,00 |
SN74AUP1T34DCKR Visão geral
A voltage-level translator (also called a level shifter) is an interface IC that connects digital blocks operating at different supply voltages, such as a 1.8 V microcontroller GPIO driving a 3.3 V peripheral. Level translators belong to the interface IC family within the broader semiconductor hierarchy, sitting alongside bus switches, transceivers, and logic buffers. The SN74AUP1T34 is a fixed-direction, non-inverting single-channel device built on TI's Advanced Ultra-Low Power (AUP) process family.
Key features include two separately configurable power rails (VCCA and VCCB can each be anywhere from 0.9 V to 3.6 V in any order), making it suitable for asymmetric translation such as 1.2 V to 3.3 V or 2.5 V to 1.8 V. The AUP architecture delivers very low dynamic power consumption and low static supply current, important for battery-powered and always-on designs. The device supports partial power-down operation via Ioff circuitry, so inputs and outputs remain high-impedance when either rail is unpowered, protecting downstream circuits during multi-rail sequencing.
Technically, the translator combines a low-voltage input stage referenced to VCCA with a push-pull output stage referenced to VCCB, reproducing the input logic level on the output with correct CMOS levels on the destination rail. Because the direction is fixed (A to B) and the logic is non-inverting, it behaves like a buffer across domains and requires no direction-control pin, simplifying board design compared with bidirectional translators such as the TXB/TXS families.
Typical applications include I2C-adjacent GPIO translation, UART and SPI signal buffering between voltage domains, enable/flag signal shifting in power-management circuits, and level adaptation in portable, wearable, and IoT boards where 1.2 V, 1.8 V, 2.5 V, and 3.3 V rails coexist.
Design tip: keep both rails within 0.9 V to 3.6 V at all times and place 0.1 uF decoupling capacitors close to both VCCA and VCCB pins; note the SC-70-5 footprint is compact, so thermal and layout effort is minimal but probe access is limited.
This page adds value beyond the TI datasheet by combining drop-in alternative cross-references, application guidance, and pricing comparison in one place.
Alternativas drop-in para SN74AUP1T34DCKR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SN74AUP1T34DCKR (mesmo formato e footprint) — diferindo em Output Type, Package, Function, Qualification, Translation Direction.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
74AUP1T34GS
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
74AUP1T34-7W
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SN74AUP1T34DCKR Especificações
| Função | 1-bit non-inverting unidirectional voltage-level translator |
| VCCA Supply Range | 0.9 V to 3.6 V |
| VCCB Supply Range | 0.9 V to 3.6 V |
| Translation Direction | Fixed, A to B |
| Tipo de saída | Push-pull (CMOS) |
| Channels / Bits | 1 |
| Output Drive Capability | 50 mA (per distributor listing) |
| Technology Family | AUP (Advanced Ultra-Low Power) |
| Partial Power-Down (Ioff) | Yes |
| Faixa de temperatura de operação | -40C to +85C |
| Encapsulamento | SC-70-5 (DCK / SOT-SC70), 5 pins |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Packing | Tape and Reel (DCKR) |
Configuração de pinos do SN74AUP1T34DCKR
| Pino 1 | VCCA — Side-A power supply (0.9 V to 3.6 V) |
| Pino 2 | GND — Ground reference for both rails |
| Pino 3 | A — Input port (referenced to VCCA) |
| Pino 4 | B — Output port (referenced to VCCB), push-pull |
| Pino 5 | VCCB — Side-B power supply (0.9 V to 3.6 V) |
Aplicações típicas
SN74AUP1T34DCKR é adequado para 6 aplicaçãos: MCU-to-Peripheral GPIO Translation, UART and SPI Signal Level Shifting, Power Management Enable and Reset Shifting, Battery-Powered Portable and Wearable Devices, Industrial Control Signal Conditioning, Mixed-Voltage Test and Instrumentation Boards.
MCU-to-Peripheral GPIO Translation
When a 1.8 V microcontroller must drive a 3.3 V peripheral input, the SN74AUP1T34DCKR bridges the domains with its independently configurable 0.9 V to 3.6 V rails: VCCA ties to the 1.8 V domain and VCCB to the 3.3 V domain. The fixed A-to-B direction matches one-way GPIO, enable, and flag signals, while the push-pull CMOS output guarantees clean full-swing logic levels at the receiving device. The Ioff partial power-down feature keeps the output high-impedance if either rail is unpowered during sequencing, protecting the peripheral. With a compact SC-70-5 footprint of roughly 2.0 mm x 1.25 mm and very low AUP static current, the translator fits directly under or beside the MCU without board-area penalty, making it a standard choice for dense digital boards.
Recomendado
UART and SPI Signal Level Shifting
UART TX/RX and SPI MOSI lines frequently cross voltage domains between a low-voltage SoC and 3.3 V modules. The SN74AUP1T34DCKR handles each unidirectional signal with one SC-70 translator, using VCCA on the driving domain and VCCB on the receiving domain, both within 0.9 V to 3.6 V. Because the output stage is a full push-pull driver rather than the weak auto-directional drivers of TXB-type devices, edges remain sharp and timing uncertainty is minimized, which matters for multi-Mbps UART and SPI clock integrity. One part per signal keeps routing short; place the 0.1 uF decoupling capacitors on both rails close to the device to preserve edge speed. This application suits tablets, wireless sensor nodes, and consumer electronics where 1.2 V, 1.8 V, and 3.3 V rails coexist.
Recomendado
Power Management Enable and Reset Shifting
Power-management ICs and supervisors often run from low-voltage rails while their enable, reset, or power-good signals must reach 3.3 V logic or vice versa. The SN74AUP1T34DCKR translates these one-way control signals with VCCA on the low-voltage control rail and VCCB on the receiving rail. The Ioff partial power-down behavior is specifically valuable here: during brownout or rail sequencing, the translator output goes high-impedance instead of back-feeding an unpowered domain, preventing spurious resets or latch-up risk. AUP ultra-low static current means the translator adds negligible load to always-on standby rails, important for battery-powered products with aggressive standby budgets. Its tiny SC-70 footprint lets designers place the translator directly beside the supervisor for short control-signal routing.
Recomendado
Battery-Powered Portable and Wearable Devices
Wearables and portable instruments combine coin-cell or single-cell Li-Ion derived rails (often 1.2 V to 1.8 V logic) with 3.3 V sensors and radios. The SN74AUP1T34DCKR's AUP process delivers very low static and dynamic supply current, directly extending battery life compared with older LVC/HC translator families. The wide 0.9 V to 3.6 V dual-rail range accommodates nearly discharged cell conditions down to 0.9 V on the input side, preserving functionality through the battery discharge curve. Partial power-down Ioff lets subsystems power off completely without bus contention. With five pins in a 2.0 mm x 1.25 mm SC-70 body and -40C to +85C operation, the device suits compact, temperature-exposed wearable and IoT form factors where every square millimeter and microamp counts.
Recomendado
Industrial Control Signal Conditioning
Industrial PLC and motor-control boards mix 3.3 V or 2.5 V controller logic with 5 V-tolerant or lower-voltage interface electronics. Within the rated 0.9 V to 3.6 V window, the SN74AUP1T34DCKR translates gate-driver enable lines, fault flags, and encoder index pulses between domains with fixed, predictable direction - an advantage in noisy environments where auto-directional translators can oscillate or misbehave. The -40C to +85C operating range covers typical industrial enclosure conditions, and the SC-70 package withstands standard reflow assembly. Designers should route translated fault flags with short traces and local decoupling to preserve noise margins; the strong push-pull output provides better immunity against coupled transients than weak open-drain style shifters commonly used on shared buses.
Recomendado
Mixed-Voltage Test and Instrumentation Boards
Bench instruments, data-acquisition front ends, and evaluation modules routinely combine 1.8 V FPGAs/MCUs with 3.3 V ADCs, DACs, and calibration interfaces. A single SN74AUP1T34DCKR per one-way signal (sample clocks, trigger lines, status flags) restores full logic swings across domains while adding negligible propagation uncertainty thanks to the deterministic push-pull path. The 0.9 V lower rail limit supports emerging sub-1 V-core controllers still referenced to 1.2 V I/O. Because each channel is a tiny SC-70 package, multi-channel designs place translators physically adjacent to each connector or IC, minimizing stub length and reflections on trigger and clock lines. This makes the part a common fit for precision ADC and DAC evaluation designs and automated test equipment signal routing.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SN74AUP1T34DCKR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | 74AUP1T34GS | 74AUP1T34-7W | SN74AUP1T34DBVR | SN74AUP1T34DRYR |
|---|---|---|---|---|---|
| Package | SC-70-5 (DCK) | SC-70-5 (SOT-353) - same footprint | SC-70-5 (SOT-353) - same footprint | SOT-23-5 (DBV) - different footprint | US/X2QFN-5 (DRY) - different footprint |
| Brand | Texas Instruments | Nexperia | Diodes Incorporated | Texas Instruments | Texas Instruments |
| Supply Range (per rail) | 0.9 V to 3.6 V | 0.9 V to 3.6 V | 0.9 V to 3.6 V | 0.9 V to 3.6 V | 0.9 V to 3.6 V |
| Direction | Fixed A to B, non-inverting | Fixed A to B, non-inverting | Fixed A to B, non-inverting | Fixed A to B, non-inverting | Fixed A to B, non-inverting |
| Partial Power-Down (Ioff) | Yes | Yes | Yes | Yes | Yes |
| Output Type | Push-pull CMOS | Push-pull CMOS | Push-pull CMOS | Push-pull CMOS | Push-pull CMOS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +125C (per family options) | -40C to +85C |
| PCB Footprint Compatible | Reference (SC-70-5) | Yes - pin-to-pin drop-in | Yes - pin-to-pin drop-in | No - SOT-23-5 land pattern | No - DRY land pattern |
Principais diferenciais
- True footprint drop-in second sources exist (vs 74AUP1T34GS)
- Deterministic push-pull drive vs auto-directional translators (vs TXB0101-type devices)
- Trade-off: fixed direction only (vs Bidirectional translators)
Notas de projeto
Place 0.1 uF ceramic decoupling capacitors within 2 mm of both VCCA (pin 1) and VCCB (pin 5), each with its own via to the ground plane; pin 2 (GND) should connect to a low-impedance ground. The SC-70-5 land pattern is small (~2.0 mm x 2.1 mm outline), so keep A and B traces short to limit stub inductance and preserve edge rates on SPI/UART lines. Per TI datasheet SCES841F, both rails must stay within 0.9 V to 3.6 V during operation for guaranteed output levels.
Do not substitute the SC-70-5 (DCK) footprint with the SOT-23-5 (DBV) variant pin-for-pin without checking the footprint: although both are 5-pin parts performing the same function, the packages differ and are not drop-in compatible. Also remember the direction is fixed from A to B - connecting the signal backwards results in non-functional translation. Finally, do not use the 50 mA distributor-listed drive figure as a continuous DC load rating; verify datasheet continuous output current limits for sustained loads such as LEDs.
Compared with auto-directional translators (TXB/TXS families), the push-pull fixed-direction SN74AUP1T34 gives deterministic drive strength and lower output impedance, reducing reflections and level degradation on longer traces. Estimated: for a typical AUP output edge and a 10 cm FR-4 trace (~0.5 ns/m propagation), keep the trace short relative to edge time to stay in lumped-element territory; for longer runs, add a small series resistor (22-33 ohm) near the driver to damp ringing. This makes the part preferable for clock and strobe lines where TXB weak drivers would round edges.
Leverage the Ioff partial power-down feature deliberately in multi-rail designs: sequencing of VCCA and VCCB is unconstrained, and outputs go high-impedance when either rail collapses, so no external isolation components are needed during power-down. AUP static current is very low, so the translator adds negligible drain to always-on standby rails - beneficial in battery products. Estimated: at microamp-level Icc, self-heating is negligible and no thermal calculation is required for this package at logic loads.
Informações de conformidade
RoHS compliant per TI product page and distributor listings. REACH, halogen-free, and conflict-minerals status not explicitly stated in retrieved data - verify on TI.com quality pages.
