TPS65193RGER - Dual High-Voltage TFT-LCD Scan Driver | TI
N.º da peça: TPS65193RGER ✓ AtivoTPS65193RGER Visão geral
A high-voltage scan driver is a specialized interface IC that transfers low-voltage timing commands from the host controller to the elevated voltages required by TFT gate lines. Its position in the display hierarchy is controller interface, then row-driver interface, then gate-line scan driver. This device does not process image data; instead, it supplies the high-voltage, charge-sharing waveforms that select and bias TFT rows.
Key features include a 35 V high output-voltage level, an output swing down to -28 V, scan-driver output charge sharing, and four logic-level inputs. The 24-VQFN package measures 4 mm on each side, supporting compact display-module designs where connector count and board area are constrained. The RGER orderable designation identifies the 4 mm x 4 mm VQFN package configuration.
Each high-voltage scan driver receives CPVx and generates two outputs, CKVx and CKVBx. A separate STV logic input produces the STVP output. Charge sharing reduces peak drive demand by transferring charge between the complementary outputs rather than driving each output as an isolated hard switch, helping lower switching loss in the gate-line drive network.
Typical applications are amorphous-silicon TFT LCD modules, including small-panel monitors, portable instruments, industrial HMIs, test equipment, and control-system displays. The device is most appropriate where the panel requires negative off-level and positive high-level gate drive but does not require a separate source-driver solution from the same device.
Designers must account for the -28 V to 35 V output range, provide suitable bypassing on the high-voltage supply rails, and validate output timing against the target TFT panel. Panel bias requirements, leakage into neighboring rows, and clock-edge placement determine whether the charge-sharing outputs provide adequate settling time.
This page consolidates the verified manufacturer and distributor information, separates documented specifications from unavailable data, and provides application guidance and comparison considerations that are not presented as a substitute for the complete Texas Instruments datasheet.
Alternativas drop-in para TPS65193RGER — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Nenhuma alternativa drop-in disponível para este produto.
Solicitar alternativasTPS65193RGER Especificações
| Product Type | Dual high-voltage TFT-LCD scan driver |
| Number of Scan Drivers | 2 |
| High Output-Voltage Level | 35 V |
| Low Output-Voltage Level | Down to -28 V |
| Output Voltage Swing | -28 V to 35 V |
| CPV Input Type | Logic-level |
| STV Input Type | Logic-level |
| High-Voltage Outputs | CKVx, CKVBx and STVP |
| Output Charge Sharing | Supported |
| Target Panel Technology | Amorphous-silicon-gate TFT LCD |
| Number of TFT-LCD Panels | 2 |
| Encapsulamento | 24-VQFN |
| Package Dimensions | 4 mm x 4 mm |
| Tipo de montagem | Surface mount |
| Logic-Level Input Count | 4 |
Guia de Configuração de Pinos do TPS65193RGER 4 mm x 4 mm
Configuração de pinos para TPS65193RGER (pacote 4 mm x 4 mm). A numeração dos pinos, funções e diagramas de conexão estão definidos no datasheet do fabricante. Consulte-o para o footprint exato e diretrizes de soldagem.
Nenhum dado detalhado de pinagem disponível para TPS65193RGER.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
TPS65193RGER é adequado para 6 aplicaçãos: Amorphous-Silicon-Gate TFT LCD Modules, Industrial HMI Touch Panels, Portable Test and Measurement Displays, Automotive Instrument Cluster Displays, Broadcast and Professional Video Monitors, Laboratory and Control-System Graphical Displays.
Amorphous-Silicon-Gate TFT LCD Modules
The TPS65193RGER is intended for amorphous-silicon-gate TFT LCD glass, where each CPVx command generates complementary CKVx and CKVBx waveforms and the STV input generates STVP. Its documented -28 V to 35 V swing addresses the elevated gate-selection and bias levels encountered in ASG panels. The 24-VQFN 4 mm x 4 mm package also conserves board area in compact display modules where connector density and EMI spacing are constrained.
Recomendado
Industrial HMI Touch Panels
Industrial human-machine interface panels commonly use TFT row-driver architectures that need high-voltage timing signals while the host controller remains at low logic levels. The TPS65193RGER provides four logic-level inputs and complementary high-voltage outputs from -28 V to 35 V, making it relevant to the gate-drive stage of an ASG display. Panel-specific timing and leakage requirements still need verification before the output-drive configuration is released for production.
Recomendado
Portable Test and Measurement Displays
Compact instruments often place the display close to high-speed analog and digital circuitry, increasing the importance of controlled gate-drive transitions. The TPS65193RGER's charge-sharing output feature can reduce peak switching demand relative to hard-driven complementary outputs, while its small 4 mm square VQFN preserves PCB area. Designers should still evaluate output edge rate, panel row leakage, and the supply-decoupling arrangement against the target display module.
Recomendado
Automotive Instrument Cluster Displays
Vehicle instrument clusters can employ TFT LCD panels whose gate driver must operate across negative and positive voltage levels. The TPS65193RGER's -28 V to 35 V output range, dual scan-driver organization, and logic-level command inputs fit the gate-drive function for compatible ASG panels. Automotive qualification, temperature range, isolation requirements, and electromagnetic-compatibility conditions are not established by the verified excerpts and must be checked separately.
Recomendado
Broadcast and Professional Video Monitors
Professional video monitors often use larger TFT panel architectures with stringent row-to-row signal-integrity requirements. The TPS65193RGER generates complementary CKV and CKVB waveforms with output charge sharing, providing a gate-drive function for compatible ASG TFT panels. Because panel timing and source-driver architecture vary, the monitor design must confirm output polarity, edge placement, bias levels, and panel leakage before adopting the device.
Recomendado
Laboratory and Control-System Graphical Displays
Laboratory instruments and programmable control panels often use compact TFT LCDs driven by a dedicated timing controller and high-voltage scan-driver network. The TPS65193RGER accepts logic-level CPV and STV commands and produces three high-voltage output functions for the gate lines. Its compact 24-VQFN footprint supports dense front-panel layouts, while engineers should verify the panel's required -28 V low level and 35 V high level during schematic review.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para TPS65193RGER — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto |
|---|---|
| Package | 24-VQFN, 4 mm x 4 mm |
| Brand | Texas Instruments |
| Product Type | Dual high-voltage TFT-LCD scan driver |
| High Output Level | 35 V |
| Low Output Level | Down to -28 V |
| Output Swing | -28 V to 35 V |
| Scan-Driver Channels | 2 |
| Logic-Level Inputs | 4 |
| Output Charge Sharing | Supported |
| Target Display Technology | Amorphous-silicon-gate TFT LCD |
Principais diferenciais
- Dedicated dual high-voltage gate-drive architecture (vs Generic TFT LCD level-shifter ICs)
- Logic-level control with high-voltage output generation (vs Host-side LCD interface controllers)
- Compact panel-oriented footprint (vs Larger-package TFT scan-driver families)
- Scan-driver output charge sharing (vs Hard-driven complementary output approaches)
Notas de projeto
Treat VON and VOFF as high-voltage rails and decouple them close to the device pins according to the manufacturer datasheet. The verified output swing of -28 V to 35 V establishes the required bias envelope, but it does not provide the allowable rail tolerances or quiescent current. Verify those limits before selecting regulators or charge-pump stages, because a supply that reaches the required amplitude but lacks current headroom can produce gate-line timing errors.
Keep the CPV and STV logic connections away from the CKV, CKVB, and STVP high-voltage outputs to minimize capacitive coupling into the timing controller. Place the required bypass capacitors at the package power pins with short ground returns, and preserve the panel's recommended trace geometry. Because the verified excerpts do not include a complete pinout or layout example, use the Texas Instruments datasheet layout rather than inferring pad locations from the package outline.
Do not assume that any similarly described TFT LCD driver is pin-compatible with the TPS65193RGER. A valid replacement must preserve the 24-VQFN footprint and the electrical meaning of every numbered pin, including the paired CPV/CKV/CKVB and STV/STVP relationships. Also avoid describing a generic LCD level-shifter IC as a drop-in equivalent; its output voltage, timing, and pin architecture may differ substantially.
Validate complementary CKV and CKVB edge timing against the target TFT panel rather than relying only on the nominal -28 V to 35 V levels. Row leakage, panel capacitance, and clock-edge placement determine whether the panel receives adequate settling time. The documented charge-sharing function reduces peak drive demand, but the correct external configuration must follow the manufacturer's typical-application circuit and the panel supplier's timing constraints.
Informações de conformidade
The supplied verified excerpts do not explicitly state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status. Compliance must be confirmed from the current manufacturer product page or the distributor compliance records.
