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V62/09628-01XB - 10-Bit 8-Ch Low-Power Serial ADC | Maxim
The Maxim Integrated (Analog Devices) V62/09628-01XB is a 10-bit, 8-channel, low-power, serial-interface analog-to-digital converter (ADC) supplied in a 20-pin SSOP (Small Shrink Small Outline Package) with gull-wing leads, qualified to the MILITARY temperature grade. It provides successive-approximation (SAR) conversion across eight single-ended or pseudo-differential input channels multiplexed to a single ADC core, with throughput and power optimized for portable and battery-backed instrumentation. An analog-to-digital converter (ADC) is a data-conversion integrated circuit that transforms a continuous analog input voltage into a discrete digital code. Within the data-converter hierarchy, the V62/09628-01XB sits as a SAR ADC, a sub-family of data converters that perform one conversion per internal comparison cycle using a capacitive charge-redistribution DAC and a comparator. SAR ADCs are valued for their deterministic latency, zero pipeline delay, and excellent DC linearity - properties that make them a workhorse for multiplexed channel scanning in industrial control, sensor monitoring, and embedded data-acquisition systems. Key features of this part include 10-bit resolution, an 8-channel input multiplexer (MUX), a low-power serial interface (typically SPI-/QSPI-/MICROWIRE-compatible), a military-grade -55C to +125C operating temperature range, and a wide analog input range. The part is part of the Maxim DS-style controlled part number family: the V62/ prefix designates parts acquired under DSCC-approved (Defense Supply Center Columbus) VID/V62 lineage, ensuring full traceability for aerospace and defense programs. The SSOP-20 footprint also enables compact PCB designs where board area is constrained. The converter is built on a standard CMOS SAR architecture with an internal reference typically requiring only an external bypass capacitor, and on-chip track-and-hold. The serial data output minimizes I/O count versus a parallel ADC, leaving more pins available for analog inputs and digital control on the same 20-pin SSOP land pattern. Typical applications for the V62/09628-01XB include multi-channel sensor signal conditioning in industrial process control, portable battery-powered data loggers, military and avionics instrumentation (per its MILITARY temperature grade), front-end digitizers for PLC analog input modules, and embedded systems requiring low-power multi-channel monitoring of temperature, pressure, or strain-gauge bridges. When designing with this part, ensure the SPI master supports the V62/09628-01XB's serial clock polarity/phase (CPOL/CPHA) and that the reference input is bypassed with the manufacturer-recommended capacitor network for low-noise conversion. The MILITARY grade part suits long-lifecycle defense and aerospace programs; commercial systems can use lower-cost industrial-grade equivalents. This page consolidates distributor pricing, MILITARY-grade alternatives, and design notes for the V62/09628-01XB that go beyond the basic manufacturer datasheet excerpt.
VSP3200Y - 16-Bit 8MSPS CCD Signal Processor | TI
The Texas Instruments VSP3200Y is a 16-bit, 8 MSPS, 3-channel analog front end (AFE) CCD signal processor with dual output mode, housed in a 48-pin LQFP (7x7 mm) package and operating from a single +5V supply. A CCD/CIS analog front end is the mixed-signal stage between an image sensor and a digital image processor. It samples tiny charge-derived pixel voltages, removes reset and kTC noise through correlated double sampling (CDS), amplifies the signal to match the ADC input range, and digitizes it. Within the signal chain hierarchy, the AFE sits between the sensor and the image-signal processor, and is a critical determinant of final image dynamic range and noise floor. Key features include an integrated triple correlated double sampler (CDS), a programmable gain amplifier with up to +13 dB gain, selectable operating modes (1-channel or 3-channel CCD mode at up to 8 MSPS), selectable normal or demultiplexed output modes, and an offset control range of +3V. The 16-bit conversion resolution preserves fine shadow detail in scanned images, essential for document and film scanners. Architecturally, the VSP3200 combines three CDS/PGA channels feeding a 16-bit ADC pipeline optimized for line-rate scanning. The demultiplexed output mode makes the device interface compatible with the VSP3210, which is pin-to-pin compatible with the VSP3100 in that mode, providing a migration path to a one-chip solution. Typical applications include flatbed document scanners, film scanners, CIS-based scanner modules, and industrial inspection cameras that use CCD or CIS sensors. Design consideration: because the part runs from a single +5V rail, keep the analog 5V supply clean and well decoupled; noise on this rail directly appears in pixel data at 16-bit resolution levels. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
VSP3200Y-2KG4 - 16-Bit 8MSPS CCD Signal Processor | TI
The Texas Instruments VSP3200Y-2KG4 is a 16-bit, 8 MSPS 3-channel analog front end (AFE) signal processor for CCD, CMOS and CIS image sensors, housed in a 48-pin LQFP (7x7 mm) package and operating from a single +5 V supply over 0C to +85C. An analog front end for image sensors is a specialized data-conversion IC that sits between a charge-coupled device (CCD) sensor and the digital image pipeline. It performs correlated double sampling (CDS) to remove kTC and low-frequency noise, applies programmable gain, offsets the black level, and digitizes the conditioned pixel signal with a high-speed ADC, delivering a clean digital video stream to downstream DSP or image-processing logic. Key features of the VSP3200Y include three independent Correlated Double Samplers (CDS) and three Programmable Gain Amplifiers (PGAs) that process CCD signal channels end-to-end on one chip, a 16-bit ADC running at up to 8 MSPS, and dual output mode for flexible system interfacing. Integration of the complete analog chain eliminates discrete CDS/PGA stages, reducing board area and analog design risk. The device is built on CMOS process technology and provides a serial digital output interface. According to TI product documentation, the VSP3200Y is interface compatible with the VSP3210, a 16-bit one-chip product; the VSP3210 is in turn pin-to-pin compatible with the VSP3100 when operated in demultiplexed output mode, giving designers a documented upgrade and substitution path within the same LQFP-48 family. Typical applications include CCD camera signal chains for industrial inspection, consumer video capture, and contact image sensor (CIS) modules used in scanners and document imaging. The single 5 V supply suits legacy 5 V consumer and industrial boards. When designing with this part, verify power-supply decoupling on both the analog and digital domains and confirm the output mode (multiplexed vs dual) matches the pixel-rate timing of your CCD clocking scheme. This page synthesizes distributor availability, drop-in family alternatives (VSP3210, VSP3200Y, VSP3100), and design considerations not found on the manufacturer product page.
WM8144CPT - 10-Bit CCD Imaging Data Converter | Texas Instruments
The Texas Instruments WM8144CPT is an integrated 10-bit data-acquisition system for imaging applications, packaged in a 27-pin CPT surface-mount package. It combines the analog signal-conditioning functions required by CCD sensors with a 10-bit ADC and optional pixel-by-pixel image compensation. The supplied source identifies WM8144CPT as an audio-channel IC, while the family description identifies WM8144 as an integrated CCD-imaging data-acquisition system. Those descriptions should be reconciled against the original manufacturer documentation before using the part in a new design. A CCD image sensor is a semiconductor that converts accumulated light into analog charge and transfers that charge through output circuitry in a sequence. Because the resulting signal is weak, noisy, and often offset or gain mismatched, imaging systems require conditioning before digital conversion. An integrated data-acquisition IC reduces discrete circuitry and helps standardize the interface between the sensor output amplifier, analog-to-digital converter, and image-processing electronics. The WM8144 family provides the core functions needed for imaging: CCD-compatible analog signal conditioning, a 10-bit ADC, and optional pixel-by-pixel compensation. Compensation circuitry is used to correct sensor-column offsets, gain variations, dark current, or fixed-pattern effects before pixels are interpreted. The practical benefit is a more compact analog section, but final image quality still depends on sensor characteristics, clocking, grounding, reference quality, and system calibration. The exact suffix CPT denotes the supplied package/orderable variant, but the verified source set does not expose the full pin list, electrical ratings, ADC conversion rate, voltage limits, clock requirements, or operating-temperature limits. Consequently, those values are not inferred here. The 27-page document count reported by a search result is a page count, not proof of the target package pin count, so it is not used to construct a pinout or package drawing. Typical imaging uses include scientific CMOS-compatible signal chains, industrial line-scan cameras, low-light surveillance modules, barcode and document scanners, machine-vision cameras, and embedded optical measurement systems. In each case, the sensor amplifier output must meet the WM8144 input range and sampling requirements. Because those limits are unavailable in the supplied data, a new design should treat them as release-gating requirements and verify them in the original datasheet. Layout is especially important because CCD outputs are high impedance and susceptible to coupling, ground noise, and reference disturbance. Place the device close to the sensor output, keep the analog path compact, isolate clocks from sensitive traces, and return unused inputs according to the verified pin documentation. Use a stable, low-noise reference and suitable bypass capacitors once their required values are confirmed from the manufacturer guidance. This page distinguishes documented WM8144-family functions from unverified target-variant specifications, lists the supplied sourcing records, and avoids fabricating pin assignments, ratings, lifecycle claims, stock levels, or prices. Engineers should download and review the original WM8144 documentation before layout release, schematic sign-off, or production procurement.
WM8501CGED - 24-Bit 192kHz Stereo Audio DAC | Cirrus Logic
The Cirrus Logic WM8501CGED is a 24-bit stereo digital-to-analog converter with a 192kHz sampling rate, DSP and I2S data interfaces, and a 14-SOIC package. It includes a 1.7Vrms line driver according to the Wolfson datasheet listing. The device is intended for high-fidelity audio playback and digital audio conversion. Its two-channel architecture supports stereo output, while the 24-bit word length and 192kHz sampling capability target high-resolution audio systems. An audio DAC is a data-conversion IC that transforms digital audio samples into analog voltage signals. In the signal chain, a digital source such as a decoder, computer, CD player, or streaming interface supplies samples to the DAC, which then drives an audio amplifier, headphones, mixer, or line input. The WM8501CGED belongs to the ADC/DAC and data-conversion IC hierarchy, specifically the special-purpose audio DAC class. The verified specifications identify a stereo DAC, 24-bit resolution, 192kHz operation, DSP and I2S interfaces, analog and digital supply sources, a 2.7V to 5.5V supply range, and a -40°C to 85°C operating-temperature range. The 1.7Vrms line driver is the key analog-output feature listed by the datasheet source. The 14-SOIC package supports conventional surface-mount PCB assembly while exposing the digital control, power, and analog connections required by the converter. Because the available verified data does not include the complete electrical timing table, pin names, pinout drawing, digital input logic levels, output distortion, dynamic range, channel separation, or recommended application circuit values, those parameters are marked as data needed rather than inferred. The 24-bit and 192kHz ratings should be treated as interface and format capabilities, not as a guarantee of end-to-end audio performance without checking the complete manufacturer documentation and analog implementation. Typical application domains include consumer audio equipment, compact digital audio systems, powered speakers, sound-bar signal paths, computer audio accessories, and legacy high-resolution playback designs. The I2S interface can connect to a suitable digital audio controller when its clocking and framing requirements match the WM8501CGED. The DSP interface provides an additional digital control path for supported audio-processing configurations, but software and register compatibility must be verified before replacement. The main design consideration is power and signal integrity. Keep the analog and digital supplies properly decoupled, route high-frequency digital clocks away from the analog output, and follow the manufacturer’s recommended land pattern and component placement when those details are available. This page combines the verified distributor classification, package and interface information, datasheet-link sources, and engineering selection guidance without adding unverified performance claims.
WM8523GEDT - 24-Bit 192kHz Stereo DAC | Cirrus Logic
Cirrus Logic WM8523GEDT is a 24-bit, 192kHz stereo digital-to-analog converter with I2C and SPI control in a 20-pin TSSOP package. It supports a 2.97V to 3.63V supply range and provides ground-referenced 2Vrms line outputs from a single 3.3V rail. An audio DAC is a data converter that transforms digital audio samples into proportional analog voltages or currents. In the signal chain, a digital-to-analog converter sits between an audio source and an analog line-output stage. Its resolution, sampling rate, interface, clocking, and output architecture determine how faithfully digital recordings can be reproduced. The WM8523GEDT uses 24-bit resolution and supports sampling rates up to 192kHz. I2C and SPI interfaces provide flexible connection to an audio processor or digital transport. Its integral charge pump supports the internal generation of negative supply voltage, while the DC servo enables ground-referenced outputs without line-output coupling capacitors and helps reduce power-on pops and clicks. Cirrus Logic describes the device as a stereo digital/analog converter with 2Vrms ground-referenced line-driver outputs. A single 3.3V supply rail simplifies system power planning. The output stage is intended for line-level audio paths, including consumer audio equipment, powered speakers, headphones through an external amplifier, and digital source components. The device also includes software-controlled configuration and an integrated low-pass filter for removing out-of-band digital noise. System design should preserve clean analog and digital return paths, provide a stable low-noise 3.3V supply, and use the supported I2C or SPI interface correctly. Output loading, grounding, and external amplifier selection remain important system-level considerations. This product data consolidates verified manufacturer and distributor information, interface characteristics, sourcing details, and practical design guidance. It is intended to help engineers evaluate the WM8523GEDT for compact, high-resolution stereo audio designs while clearly separating verified facts from parameters that require additional datasheet or design confirmation.
WM8725CGED - 24-Bit Stereo Audio DAC | Cirrus Logic
The Cirrus Logic WM8725CGED is a 24-bit stereo audio digital-to-analog converter with a 96 kHz sampling rate, selectable normal or I2S-compatible serial input, and a 14-pin SOIC package. According to the verified distributor listing, it is designed as a special-purpose audio DAC and provides an excellent 99 dB signal-to-noise performance. The WM8725 belongs to the audio DAC hierarchy: digital-to-analog converter, audio converter, data-acquisition and signal-conversion integrated circuit. Its function is to convert digital audio samples into left and right analog output signals while preserving low-noise performance for portable audio equipment, video CD players, and related consumer audio systems. The selectable serial interface supports 16-bit to 24-bit digital input formats, while integrated digital filtering helps shape the conversion output. Key verified features include stereo DAC operation, 24-bit resolution, 96 kHz operation, normal or I2S-compatible serial data interfaces, and 99 dB signal-to-noise performance. The 14-SOIC package is appropriate for conventional surface-mount PCB assembly. Exact supply-voltage limits, analog output specifications, clock requirements, filter characteristics, and electrical operating limits were not included in the supplied source text and are therefore not inferred here. The device architecture combines a digital input interface, digital filtering, and sigma-delta DAC stages. This arrangement is suitable when a system accepts digital audio from a decoder, portable player, or digital audio processor and requires analog stereo outputs. The 99 dB SNR figure provides a concrete selection criterion when comparing audio-conversion stages, although system-level noise also depends on the supply, clock, analog output network, grounding, and downstream amplifier. Typical applications include portable audio equipment, video CD players, digital audio adapters, compact stereo systems, and embedded audio products. In each case, the important design question is whether the required input word length, sample rate, interface mode, supply arrangement, and analog output topology match the device and its application circuit. A key design consideration is to preserve clean analog and digital grounding while keeping the digital interface and clock signals away from sensitive analog output paths. Decoupling and output filtering should follow the manufacturer application guidance once the complete electrical data is available. This page synthesizes the verified distributor specifications, source links, and engineering context rather than adding unverified datasheet values. The verified distributor records identify Cirrus Logic as the current source brand and describe WM8725CGED as a 24-bit, 96 kHz, stereo, 14-SOIC audio DAC. LCSC also reports the part as in stock with a listed price of $1.0043, while current quantity pricing beyond that single source is not provided.
WM8762CGED - 24-Bit 192kHz Stereo DAC | Cirrus Logic
Cirrus Logic WM8762CGED is a 24-bit stereo digital-to-analog converter IC operating up to 192 kHz and housed in an 8-pin SOIC package. Verified distributor data identifies it as a serial audio DAC with a 24-bit resolution, 192 kHz capability, and an 8-SOIC format. A DAC is a data-conversion semiconductor that transforms digital audio samples into left- and right-channel analog voltages. In the signal hierarchy, the WM8762CGED belongs to the digital-to-analog converter class, then to the ADC/DAC family and the broader signal-conversion and audio interface categories. Its stereo outputs are suited to audio playback paths in consumer, communications, and embedded audio systems. The verified data identifies three headline characteristics: 24-bit resolution, support for operation up to 192 kHz, and an 8-pin SOIC package. These values position the converter for designs requiring higher-resolution digital audio and a compact surface-mount footprint. The serial interface and stereo output architecture allow a digital audio source to feed two analog channels through one converter IC. The WM8762CGED family is identified in distributor listings as a Wolfson/Cirrus Logic audio DAC. Its practical implementation depends on the host audio interface, clocking scheme, analog output network, supply arrangement, and the format expected by the connected digital source. Exact pin names, voltage ratings, output architecture, and supported digital audio formats require confirmation from the manufacturer datasheet before PCB or firmware design. Typical audio uses include digital audio players, multimedia systems, communications equipment, and embedded sound-control platforms. In a player design, the converter would typically sit between the digital audio processor and an analog output stage feeding headphones or a line-input amplifier. The compact SOIC package can simplify routing where a small surface-mount footprint is important. Designers should verify the datasheet pinout, recommended decoupling, clock requirements, analog output connection, and supported operating conditions. Since the supplied data does not state supply voltage, pin functions, output mode, or digital interface details, those values are intentionally marked as data needed rather than inferred. This page separates verified distributor facts from engineering information that still requires datasheet confirmation. This page consolidates verified distributor references, package identity, audio-resolution information, and selection guidance. It does not treat generic cross-reference results as proof of drop-in replacement; engineering equivalence must be confirmed by package, pinout, electrical limits, and digital-interface compatibility.
WM8783GED/V Stereo 98kHz Audio ADC | Cirrus Logic
Cirrus Logic WM8783GED/V is a stereo low-power audio analog-to-digital converter with a 98 kHz sampling rate and 24-bit I2S output, supplied in an 8-pin SOIC package. The verified manufacturer-family source describes it as a stereo low-power ADC, while the retrieved distributor data identifies the same device family for 96 kHz operation. It is designed for compact audio capture, playback, and mixed-signal systems requiring dual-channel conversion. An ADC is an analog-to-digital converter, a mixed-signal integrated circuit that converts continuously varying analog audio voltages into digital samples. In the broader component hierarchy, an audio ADC belongs to data converters, mixed-signal semiconductors, and signal-chain ICs. The WM8783GED/V therefore sits between an analog microphone or line input and a digital audio interface such as I2S. The principal verified features are stereo operation, a 24-bit conversion format, I2S digital output, and a family sampling-rate capability reported as 98 kHz in distributor material and 96 kHz in the Wolfson-family result. The device is identified as low power, making it relevant to embedded audio systems where power consumption, channel count, and board area constrain the architecture. The manufacturer-family datasheet source also indicates that the device is manufactured on a CMOS process and is ESD-sensitive. WM8783GED/V is suitable for digital recording front ends, USB audio adapters, industrial audio capture, portable audio equipment, and consumer audio systems. In each case, the stereo ADC can convert left and right analog inputs into digital samples for downstream processing or transmission. The I2S interface helps simplify connection to digital audio controllers, DSPs, and microcontrollers, although the host device must support the required clocking and framing format. When selecting this part, verify the exact electrical characteristics, analog input range, clock requirements, master or slave operating mode, and package pin assignment in the current manufacturer documentation. Do not infer those values from generic ADC descriptions. For replacement work, confirm that the candidate uses the same SOIC footprint and pin-to-pin signal arrangement rather than relying only on a similar sample rate or converter function. This page combines the verified source snippets for the WM8783GED/V family with engineering-oriented application and selection context. Because the retrieved data does not provide a complete current manufacturer product page, several detailed parameters remain explicitly marked for verification rather than being guessed.
X9313UST1 - 50kΩ 32-Tap Digital Potentiometer SOIC-8 | Renesas
The Renesas X9313UST1 is a digitally controlled potentiometer (XDCP™) housed in an 8-pin SOIC package with a fixed end-to-end resistance of 50 kΩ and 32 resistive taps. It provides a single-channel, non-volatile, up/down wiper interface through three logic input pins (U/D, INC, CS) and stores the last wiper position through on-chip nonvolatile memory that retains setting across power cycles. The 32-tap resolution gives approximately 1.0% per-step resolution across the resistor array. Background context: a digital potentiometer (often abbreviated "digi-pot") is a solid-state, semiconductor replacement for a mechanical potentiometer or trim pot. Digi-pots sit within the broader data-acquisition and analog-signal-conditioning hierarchy, alongside DACs and digital rheostats, and they belong to the Renesas XDCP™ family. Unlike mechanical pots, they are programmable by host firmware, never wear from mechanical actuation, and ship in surface-mount packages suitable for reflow soldering and dense PCB layouts. Key features include a low 1 mA (typical) standby current, terminal voltages up to ±5 V across the resistor array, a 1.0% end-to-end resistance tolerance, and a wiper current rating up to approximately ±1 mA continuous, with peak surge handling to 10 mA. The 3-wire serial interface consumes only three MCU GPIO pins and is compatible with 5 V logic. The internal architecture pairs a polysilicon resistor array with CMOS wiper switches and a non-volatile memory cell that latches the last wiper position before power-down. Three control inputs (CS, INC, U/D) implement a step-and-direction interface: CS enables the chip, INC clocks each tap step, and U/D selects up or down direction. Power-on recall places the wiper on the stored value with deterministic behavior. Typical applications are audio volume/balance control, LCD contrast/brightness trimming, programmable voltage references, sensor calibration, and parameter-set storage where an MCU must hold a setting through power-down. Because the wiper retains state without external EEPROM, designers can eliminate a serial EEPROM and reduce BOM cost in many calibration circuits. When designing with the X9313UST1, respect the maximum terminal voltage (±5 V across the resistor terminals) and verify that pin 8 is correctly identified in PCB layout - the part is widely second-sourced and a small number of look-alike 8-pin digi-pots swap the GND and VL pin positions. Add a 0.1 µF decoupling capacitor close to the supply pin and confirm that CS is not allowed to float. This page combines the Renesas datasheet specifications, current distributor pricing, pin-compatible cross references, and practical layout notes not always covered in the original datasheet, providing engineers a single-page engineering brief for the X9313UST1.
XR4151CP-F - V/F Converter, 8-22V, 100kHz | MaxLinear
The MaxLinear XR4151CP-F is a monolithic voltage-to-frequency (V/F) and frequency-to-voltage (F/V) converter IC supplied in an 8-pin PDIP through-hole package. It accepts a single-ended analog input voltage of 0 to 10 V (or -10 V to 0 V with appropriate biasing) and produces a proportional output pulse train whose frequency is linearly related to the input amplitude. The maximum full-scale frequency is 100 kHz with a usable range of 1 Hz to 100 kHz and a typical linearity error of +/-0.05%. A voltage-to-frequency converter (V/F or VFC) is a mixed-signal building block that translates a continuous analog voltage into a stream of digital pulses whose repetition rate is precisely proportional to the input magnitude. VFCs sit within the broader hierarchy of analog-to-digital conversion techniques alongside successive-approximation ADCs, dual-slope integrating ADCs, and sigma-delta modulators, and are valued for their inherent monotonicity, excellent noise rejection, and galvanic isolation-friendly pulse output that can be transmitted through optocouplers or long cables. Key features of the XR4151CP-F include a supply voltage range of 8 V to 22 V, very high noise rejection, inherent monotonicity over the full dynamic range, a single open-collector output stage that can interface with CMOS/TTL logic, and the ability to operate in reverse as a frequency-to-voltage converter with a small number of external components. The -F suffix denotes the lead-free, RoHS-compliant version of the original XR4151CP, while both share the same die and pinout. The internal architecture consists of a precision current source, a high-gain operational amplifier, a comparator, and a one-shot timing network. The op-amp drives a current into an external RC network whose charging time determines output pulse width; this architecture eliminates the missing-pulse and non-monotonic errors that plague simple charge-pump VFCs. The dedicated low-leakage input protection on pin 7 prevents the inverting input from being driven below ground, eliminating the need for an external clamp diode in most applications. Typical applications include precision analog-to-digital conversion where the output is fed to a counter or microcontroller capture input, isolated analog signal transmission across 4-20 mA replacement links, motor speed control via frequency-to-voltage conversion of tachometer pulses, and long-integral analog signal conditioning in industrial weighing, temperature, and pressure transmitters. When designing with the XR4151CP-F, choose the external timing resistor and capacitor first - the resistor sets the input current range and full-scale frequency, while the capacitor sets the one-shot pulse width. Add a 0.01 uF bypass capacitor close to the supply pin and use low-leakage timing components to maintain the 0.05% linearity specification. This page synthesizes distributor pricing, lead-time, pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single-source decision framework for new designs and legacy XR4151CP replacement.
XRD8775AID-F - 8-Bit 20MSPS Flash ADC, 5V CMOS | MaxLinear
The MaxLinear (formerly Exar) XRD8775AID-F is an 8-bit, 20 MSPS analog-to-digital converter using a 2-step flash architecture in a 20-pin SOIC wide-body package. It operates from a single 5V supply, accepts analog inputs from 0V to VDD, supports a reference range of 1V to VDD, and integrates an internal sample-and-hold function that eliminates the need for an external track-and-hold amplifier. Typical power consumption is 75 mW (excluding reference current), enabling low-power system designs. An analog-to-digital converter (ADC) is a data converter that translates real-world continuous analog signals into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Flash and 2-step flash ADCs achieve the highest sampling rates among all ADC architectures by using parallel comparator banks, making them well-suited for video, instrumentation, and high-speed control loops. The XRD8775AID-F belongs to the hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key specifications include 8-bit resolution, 20 MSPS sampling rate, parallel digital interface, single 5V analog supply, internal S/H, 0V-to-VDD analog input range, and -40C to +85C operating temperature. The wide-body 20-SOIC package (0.295 inch / 7.50 mm width) provides robust thermal performance and ease of hand-soldering for prototyping. The part is offered in tube packaging for manufacturing. The 2-step flash architecture trades a small number of comparator channels for a substantial reduction in die area and power consumption versus a full flash design, while still maintaining video-grade 20 MSPS throughput. Internal S/H bandwidth supports IF undersampling and video bandwidth applications. The CMOS process ensures low power, latch-up free operation, and stable performance across the industrial temperature range. Typical applications include video digitisation, CCD camera front ends, digital oscilloscopes, ultrasound front-end preprocessing, IF sampling in communications receivers, and industrial process control loops. The combination of wide analog input range and integrated S/H simplifies board-level design for low-channel-count high-speed data acquisition. When designing with this part, place a 0.1 uF ceramic decoupling capacitor as close as possible to the VDD pin and a bulk tantalum or electrolytic capacitor on the analog supply rail. The reference pin requires a low-impedance source; use an op-amp buffer or a dedicated reference IC if the application demands better than 8-bit absolute accuracy. This page synthesises distributor pricing, parametric drop-in alternatives from same-brand and cross-brand portfolios, and practical design notes that complement but do not duplicate the manufacturer datasheet.
XRD8775AIU - 8-Bit 20MSPS Flash ADC, 20-SSOP | MaxLinear
The MaxLinear (formerly Exar) XRD8775AIU is a monolithic CMOS 8-bit flash analog-to-digital converter delivering up to 20 MHz sampling rate in a 20-pin SSOP package. It integrates an internal sample-and-hold amplifier, operates from a single +5 V supply, and consumes only 75 mW typical (excluding external reference current). The input voltage range spans 0 V to VDD with a flexible reference voltage range of 1 V to VDD, allowing direct interface with single-supply analog signal chains. An 8-bit flash ADC is a parallel-architecture converter that uses 2^N-1 comparators to digitize an analog input in a single clock cycle, delivering the fastest conversion latency of any ADC topology at the cost of exponential die-area growth with resolution. Flash converters therefore dominate sub-10-bit, multi-MHz applications such as video digitizers, digital oscilloscope front ends, and radar IF samplers where latency and sampling rate, not resolution, are the primary constraints. Key specifications of the XRD8775AIU include 8-bit resolution, 20 MSPS maximum sampling rate, internal S/H, single +5 V supply operation, 75 mW typical power dissipation, latch-up-free CMOS construction, and 2000 V minimum ESD protection. The parallel data interface simplifies connection to FPGAs, ASICs, or microcontrollers without requiring a serial programming sequence. The 20-SSOP package suits space-constrained boards where analog and digital grounds can be partitioned for noise immunity. Architecturally, the device uses 255 parallel latched comparators feeding a priority encoder that generates an 8-bit thermometric code, then a binary encoder delivers the output word in a single clock edge. The internal sample-and-hold amplifier stabilizes the input within the aperture window, which is critical for full-scale inputs above 10 MHz to avoid code-edge distortion. The reference ladder is externally driven, giving the designer freedom to set the LSB size by scaling VREF between 1 V and VDD. Typical applications include digital oscilloscope input channels, video digitizers, CCD imaging front ends, radar IF sampling, ultrasound beamforming pre-processors, and industrial data-acquisition front ends. The 75 mW dissipation also suits portable test gear and battery-powered instrumentation where the internal S/H eliminates an external track-and-hold IC. Design tip: Place a 0.1 uF ceramic decoupling capacitor within 5 mm of the VDD pin and a bulk 10 uF tantalum capacitor near the analog ground island; route the 8-bit parallel bus with matched trace lengths to prevent sub-LSB timing skew at the full 20 MSPS rate. Also bypass the external VREF pin with 10 uF to keep the internal resistor ladder stable and reduce sparkle-code errors. This page synthesizes distributor pricing, verified drop-in 8-bit flash ADC alternatives, and practical PCB layout guidance that goes beyond the manufacturer datasheet, helping engineers shorten the BOM-sourcing and design-in cycle for this legacy flash converter.
XRD8775AIU-F - 8-Bit 20MSPS Parallel ADC | MaxLinear | Exar
The MaxLinear XRD8775AIU-F is an 8-bit resolution, 20MSPS sampling rate analog-to-digital converter (ADC) with a single-ended input and parallel digital data interface, housed in a 20-pin SSOP package. Originally introduced by Exar Corporation and now sold under MaxLinear, the part is specified as IC ADC 8BIT PAR 20MSPS 20SSOP and operates from a single 5V analog supply. An analog-to-digital converter (ADC) is a data-acquisition integrated circuit that samples continuous analog signals and converts them into discrete digital codes. Flash ADCs like the XRD8775AIU-F use an array of comparators to deliver the fastest conversion times, typically reserved for video, instrumentation, and high-speed control loops where sub-microsecond conversion latency is mandatory. The 8-bit, 20MSPS segment sits at the entry level of high-speed conversion and is well suited for digitizing video bandwidths, IF signals, and oversampled measurement channels. Key features per the manufacturer datasheet include 8-bit resolution, 20 MHz maximum sampling rate, an internal sample-and-hold (S/H) function, a single-ended analog input range of 0V to VDD, a reference input range of 1V to VDD, and typical power consumption of 75 mW (excluding reference current). The device provides latch-up free operation and ESD protection rated at 2000V minimum, simplifying board-level robustness. The XRD8775AIU-F uses a flash converter architecture with a 1:1 S/H-to-ADC ratio, providing a single simultaneous sampling channel with a parallel 8-bit output bus. This architecture removes the need for an external track-and-hold amplifier in most digitizer front ends and simplifies downstream FPGA or ASIC capture logic. Typical applications include standard-definition video digitizers, CCD/camera signal chains, ultrasound front-end signal conditioning, IF sampling for communications receivers, and high-speed industrial inspection systems. The 20MSPS capability comfortably handles component video and baseband IF signals up to about 7 MHz of input bandwidth. When designing with this part, ensure the analog input drive network presents low source impedance at the Nyquist frequency and that the reference pin is decoupled with a low-ESR capacitor placed within 5 mm of the package pin. Because the part is sourced via MaxLinear (after the Exar acquisition) and is listed as obsolete in some distributor databases, confirm long-term supply before committing to high-volume production.
XRD8785AID-F - 8-Bit 20MHz Flash ADC, 24-SOIC | MaxLinear
The MaxLinear (formerly Exar) XRD8785AID-F is an 8-bit, 20 MSPS flash analog-to-digital converter (ADC) with one input channel, housed in a 24-pin SOIC wide-body package. It uses an advanced 5V CMOS process and provides 8-bit resolution, up to 20 MHz sampling rate, an internal sample-and-hold function, and a single 5V analog supply. The device accepts an input range of 0V to VDD and a reference range of 1V to VDD, making it suitable for general-purpose digitizing of unipolar signals. Latch-up free operation and a minimum 2 kV ESD protection rating ensure robust real-world handling during board assembly and field use. An 8-bit flash ADC is the fastest ADC architecture, using 2^8 (256) parallel comparator-latch cells and a resistor reference ladder to convert an input voltage to a digital code in a single clock cycle. Flash ADCs occupy the low-resolution, very-high-speed corner of the converter family tree: SAR ADCs (successive approximation) offer higher resolution at lower speed, while pipelined ADCs sit between them. Flash ADCs therefore dominate in digital oscilloscopes, video digitizers, CCD imaging front-ends, radar IF sampling, and digital receiver IF strips where sub-100 ns latency matters more than 12-16 bit precision. Key features of the XRD8785AID-F include 5V single-supply operation, a typical power dissipation of 75 mW excluding the reference current, an internal S/H that removes the need for an external track-and-hold amplifier, and three-state CMOS-compatible digital outputs. Its flash topology delivers full-code conversion in a single clock, and the 24-SOIC package exposes all digital outputs and the S/H control pins for easy parallel interfacing to FPGAs, microcontrollers, or display controllers. Typical applications for the XRD8785AID-F include digital oscilloscope front-ends, video digitizers, CCD imaging signal chains, instrumentation digitizers, and communication IF sampling. The simple 5V/CMOS interface, parallel output bus, and low 75 mW dissipation also suit it for board-level prototyping where a fast acquisition path is needed without the cost of a precision ADC. When designing with this device, follow the datasheet's recommended decoupling and reference bypassing carefully. Place a 0.1 uF ceramic bypass close to the analog supply pin and a 10 uF bulk tantalum or ceramic capacitor nearby; bypass the reference pin with a low-impedance capacitor so the high-speed comparator ladder does not see reference bounce. For engineers evaluating the XRD8785AID-F, DigiKey, Mouser, and Octopart list it as an active MaxLinear SKU with multiple distributor stocks, while legacy Exar datasheet PDFs remain valid references. This page goes beyond the basic datasheet by consolidating distributor pricing tiers, cross-brand drop-in alternatives, and practical PCB/thermal layout notes.
XRD8785AIDTR-F - 8-Bit 20MSPS Flash ADC, 24-SOIC | MaxLinear
The MaxLinear XRD8785AIDTR-F is an 8-bit flash analog-to-digital converter (ADC) sampling at up to 20 MSPS with a single 5V supply, housed in a 24-pin wide-body SOIC package (0.295 inch / 7.50 mm body width) shipped on tape and reel. Key electrical parameters include 8-bit resolution, 20 MHz maximum sampling rate, one single-ended analog input, internal sample-and-hold (S/H), external or internal reference option, 0V-to-VDD analog input range, 1V-to-VDD reference range, 75 mW typical power consumption (excluding reference), and an operating temperature range of -40C to +85C. The suffix "D" indicates the 24-SOIC package, "T" indicates tape-and-reel packaging, and "R-F" denotes the MaxLinear / Exar part-numbering convention. A flash ADC is a type of analog-to-digital converter that uses a parallel bank of 2^n comparators to convert an analog signal to an n-bit digital code in a single clock cycle, achieving the highest sampling speed of any ADC architecture. The hierarchy is: ADC -> data converter -> data acquisition IC -> mixed-signal IC -> semiconductor. Flash converters excel in applications demanding low latency and wide input bandwidth, but they trade resolution and power efficiency against sampling speed. The XRD8785AIDTR-F occupies the entry-level 8-bit, 20 MSPS tier, which is the typical sweet spot for video digitisation, ultrasound receive beams, and intermediate-frequency (IF) sampling in low-cost communications receivers. Key features of this device include a parallel (TTL-compatible) digital output bus, internal S/H front-end, latch-up free CMOS construction, ESD protection on analog and digital pins, single 5V supply operation, and low power consumption at 75 mW typical. The 24-SOIC wide-body package measures approximately 15.4 mm x 7.5 mm x 2.35 mm, providing generous die-to-board clearance for through-hole or socketed prototypes. The device is built on a 5V CMOS process, providing low power consumption, latch-up immunity, and ESD protection. Internal reference mode simplifies bill-of-materials, while external reference mode lets designers optimise linearity or temperature drift for instrumentation-grade designs. Typical applications include video digitisation, digital oscilloscope front-ends, IF sampling in communications receivers, CCD/CMOS image sensor digitisation, and industrial control loop sampling. When designing with this device, ensure the analog input signal is bandwidth-limited to less than the Nyquist frequency (10 MHz for 20 MSPS) and that the external reference decoupling capacitor is placed within 5 mm of the REF pin to prevent kickback noise from corrupting the conversion. This page synthesises distributor stock, lifecycle risk, drop-in ADC alternatives, and practical design notes not found in the manufacturer datasheet.
XRD8799AIQ - 10-Bit 2MSPS 8-Ch ADC | MaxLinear/Exar | 44-PQFP
The MaxLinear XRD8799AIQ (originally Exar) is a 10-bit resolution, 2 MSPS pipelined analog-to-digital converter with an integrated 8-channel analog input multiplexer, housed in a 44-pin PQFP (10x10 mm) package. It combines low-power CMOS operation (35 mW typical active, 0.8 mW in power-down) with a wide input range spanning GND to VDD, eliminating the need for external signal-conditioning scaling on most signals. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a defined sample rate. The XRD8799AIQ belongs to the multi-channel, low-power successive-approximation/pipelined ADC family - a category that sits inside the broader hierarchy of data converter -> data acquisition IC -> mixed-signal semiconductor. It is purpose-built for systems that must digitize multiple analog sources while staying within strict power and board-area budgets. Key differentiating specifications include 10-bit resolution, a 2 MHz maximum sampling rate, eight single-ended input channels routed through an on-chip mux, parallel digital output, and an input range that accepts rail-to-rail signals without external scaling. A built-in power-down mode drops consumption to 0.8 mW typical, and the device does not require an external sample-and-hold for analog signals below 100 kHz or for CCD-type signals, simplifying the analog front end and BOM cost. Architecturally, the converter uses a pipelined topology that distributes conversion work across multiple low-resolution stages, achieving higher throughput than pure SAR architectures at comparable power. The integrated 8-channel mux eliminates an external analog switch tree, reducing board space, leakage paths, and channel-to-channel crosstalk sources. The PQFP-44 package gives a generous thermal pad and 10 mm x 10 mm footprint suitable for both hand-solderable prototyping and SMT production. Typical applications include CCD signal acquisition in industrial imaging, multi-sensor data logging in process control, portable instrumentation with battery operation, and mixed-signal front ends for embedded controllers. Industrial multi-channel data-acquisition boards and portable medical monitoring devices frequently select this part for its combination of throughput and low quiescent draw. When designing with the XRD8799AIQ, note that input signals below 100 kHz do not need an external track-and-hold, but faster signals should be buffered to maintain dynamic performance. Place a 0.1 uF decoupling capacitor close to each supply pin and follow the manufacturer's reference ground layout to keep digital switching noise out of the analog path. This page synthesizes distributor pricing, pin-compatible alternatives, and practical layout notes not consolidated in the manufacturer datasheet.
XRD87L75AID-F - 8-Bit 10MSPS ADC | 20-SOIC | MaxLinear
The MaxLinear (formerly Exar) XRD87L75AID-F is a low-voltage CMOS 8-bit analog-to-digital converter with a maximum sampling rate of 10 MSPS, an internal sample-and-hold, and a single 3.3V supply rail. It is housed in a 20-pin SOIC (0.295 inch / 7.50 mm body width, D-suffix package) and is provided in tube packaging per the -F factory suffix. An 8-bit flash ADC is a type of analog-to-digital converter that uses a parallel bank of 2^n comparators to convert an input voltage into a digital code in a single clock cycle, achieving the fastest possible conversion latency at moderate resolution. Within the broader signal-chain taxonomy, the XRD87L75AID-F sits between a traditional sample-and-hold stage and a digital host (FPGA, ASIC, or microcontroller), and is a member of the speed-optimized, low-resolution ADC family used for video, instrumentation, and IF digitisation. Key features include 8-bit resolution, a 10 MHz typical sampling rate, an internal track-and-hold, an analog input range of 0V to VDD, a reference input range of 1V to VDD, and typical power dissipation of 25 mW (excluding reference current). The device is latch-up free, operates from a single 3.3V supply, and uses a parallel CMOS-compatible digital interface, which simplifies connection to modern MCUs and FPGAs without external level shifters. The device is built on an advanced 3.3V CMOS process and uses a flash architecture to deliver 10 MSPS conversion speeds. Its internal S/H function guarantees a stable sample window across rapidly-changing inputs and avoids the need for external S/H circuitry, simplifying the analog front-end. Typical applications include video digitisation, CCD imaging front-ends, digital oscilloscope front-ends, IF sampling in communications, portable instrumentation, and general-purpose high-speed data acquisition. The wide analog input range (0V to VDD) lets designers digitise single-ended signals without external attenuators. When designing with this device, ensure the analog input is properly driven (low-impedance buffer recommended) and that the reference decoupling is solid. The single 3.3V supply simplifies the power tree but requires that downstream digital logic be 3.3V tolerant. This page synthesises distributor pricing, drop-in alternatives (including the SSOP-packaged variant XRD87L75AIU-F), and practical design notes that complement the manufacturer datasheet.
XRD87L75AIP-F - 8-Bit 10MSPS ADC, 20-Pin PDIP | MaxLinear
The MaxLinear XRD87L75AIP-F is a low-voltage CMOS 8-bit high-speed analog-to-digital converter with a 10 MHz sampling rate, housed in a 20-pin PDIP through-hole package. It features a single 3.3 V supply rail, an internal sample-and-hold function, an analog input range of 0 V to VDD, and a reference input range of 1 V to VDD, achieving typical power dissipation of 25 mW excluding the external reference. What is an 8-bit ADC? An analog-to-digital converter (ADC) is a data converter that samples a continuous analog waveform and produces a discrete digital code proportional to the input voltage at each clock edge. 8-bit ADCs deliver 256 discrete codes (1 LSB = full-scale / 256), which suits digital instrumentation, video digitizing, and digital oscilloscope front ends where 8-bit dynamic range is sufficient. Within the data-converter hierarchy, an 8-bit ADC sits below SAR and pipelined converters in resolution but above flash converters in speed and below the latest 12-/14-/16-bit parts in accuracy. The 10 MSPS sampling rate places this part in the legacy high-speed, low-resolution tier used in CRT digitizers, image scanners, ultrasound receive channels, and digital IF processing. Key features include latch-up free CMOS construction, parallel digital output, single 3.3 V supply operation, internal S/H function, and a wide reference input voltage range from 1 V to VDD for design flexibility. The 2-step flash architecture minimizes comparator count while delivering 10 MSPS throughput, and the part is offered as a Pb-free (RoHS-compliant) 20-pin PDIP variant suitable for industrial, instrumentation, and test-equipment applications. The XRD87L75AIP-F integrates the input track-and-hold, reference buffer, and decoding logic on a single CMOS die, allowing direct connection to a microcontroller or DSP data bus. The 25 mW typical power consumption (excluding reference) supports portable and battery-powered instruments. The 3.3 V single supply also matches CMOS logic families, simplifying interface to FPGAs and microcontrollers without level translation. Typical applications include digital oscilloscope front ends, video digitizers, ultrasound imaging receive channels, point-of-sale barcode scanners, and industrial process control data acquisition. The wide 0 V to VDD input range allows direct sampling of single-ended signals without external signal conditioning. When designing with this part, place a 0.1 uF bypass capacitor close to the VDD pin and ensure the reference input is driven by a low-impedance source. For best linearity, route CLK and digital outputs away from the analog inputs to minimize crosstalk. This page synthesizes distributor stock levels, parametric alternatives from web cross-reference search, and engineering design notes not consolidated on the manufacturer datasheet, providing unique research value for engineers selecting a legacy 8-bit ADC.
XRD87L75AIU - 8-Bit 10MSPS ADC, 3.3V, SSOP-20 | MaxLinear
The MaxLinear XRD87L75AIU is a low-voltage, CMOS, 8-bit, high-speed analog-to-digital converter (ADC) with a 10 MSPS sampling rate, packaged in a 20-pin SSOP. Operating from a single 3.3 V supply, it features an internal sample-and-hold function, an analog input range of 0 V to VDD, and a reference input range of 1 V to VDD, dissipating a typical 25 mW (excluding reference current). What is an 8-bit ADC? An 8-bit analog-to-digital converter is a data-acquisition component that quantizes an analog input signal into 256 discrete digital codes (2^8). ADC components sit in the signal chain hierarchy: ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor. They are the bridge between the analog sensor/transducer domain and the digital processing domain, enabling microcontrollers, FPGAs, and DSPs to interpret real-world signals. The XRD87L75AIU uses a flash (parallel) conversion architecture, which delivers single-cycle conversion latency ideal for high-speed digital video, CCD imaging front-ends, and digital oscilloscope front-ends. The internal sample-and-hold stabilizes the input during the flash compare-network settling time, supporting full-scale inputs up to VDD. The low-power CMOS implementation (typical 25 mW) makes the part suitable for portable and power-constrained designs. The 3.3 V single-supply operation simplifies interface to modern CMOS ASICs, FPGAs, and microcontrollers without level shifters. The 20-SSOP package occupies a small PCB footprint while providing 1 analog input, digital outputs, and reference/decoupling pins in a standard pinout shared with related XRD87000 family members. Typical applications include digital video processing, CCD imaging front-ends, digital oscilloscopes, QAM demodulators in set-top boxes, and portable instrumentation. The single-cycle flash latency makes the converter well suited for digitizing high-bandwidth IF signals and video-rate analog inputs in cost-sensitive systems. When designing with this part, place a 0.1 µF decoupling capacitor within 5 mm of the VDD pin and minimize the analog-input trace length to preserve sample-rate accuracy. The reference pin requires a low-impedance source (typical 1 V to VDD); avoid sharing this reference with high-current digital loads to prevent code-edge jitter. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
XRD87L75AIUTR-F - 8-Bit 10MSPS Flash ADC, 20-SSOP | MaxLinear
The MaxLinear XRD87L75AIUTR-F (originally Exar Corporation) is an 8-bit resolution, 10 MSPS analog-to-digital converter built on a 2-step flash architecture with an internal sample-and-hold, packaged in a 20-pin SSOP (0.209 inch / 5.30 mm width) with tape-and-reel packaging. It operates from a single 3.3 V supply, accepts a single-ended analog input from 0 V to VDD, and provides an external reference input range of 1 V to VDD for flexible full-scale setting. An ADC (Analog-to-Digital Converter) is a data acquisition integrated circuit that converts continuous analog signals into discrete binary codes at a defined sampling rate. Within the broader hierarchy, this device sits as: ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor. The 2-step flash architecture is a variant of the flash ADC that halves the comparator count versus a full flash, reducing both die cost and input capacitance, while the integrated S/H eliminates the need for an external track-and-hold amplifier in most applications. Key features include 8-bit resolution at 10 MHz sampling rate, single 3.3 V supply operation with 25 mW typical power dissipation (excluding external reference current), parallel digital output interface for direct connection to microcontrollers, DSPs, or FPGAs, and latch-up free CMOS construction for robust ESD/handling performance. The internal sample-and-hold eliminates external S/H requirements and supports full Nyquist bandwidth input frequencies, making the device suitable for general-purpose digitizing tasks where cost-per-channel matters. The XRD87L75AIUTR-F architecture uses a 2-step flash topology with on-chip S/H, error correction, and a parallel CMOS-compatible output bus. Its low input capacitance and high input bandwidth reduce drive-amplifier loading, and the part is specified to operate from a single 3.3 V rail, simplifying power tree design in 3.3 V logic systems. The internal reference buffer accepts a user-supplied reference from 1 V to VDD for system-level gain calibration. The -F suffix denotes the lead-free, RoHS-compliant tape-and-reel packaging option. Typical applications include video digitizing and graphics capture, CCD/CIS sensor front-ends, digital oscilloscope front-ends, baseband IF sampling, low-cost digital imaging, and portable instrumentation. The 8-bit/10 MSPS combination aligns well with standard-definition video bandwidths (~5 MHz) and consumer imaging throughput requirements. When designing with this part, place the input RC anti-alias filter directly at the analog input pin and provide a low-impedance reference buffer because the reference pin input current scales with sampling rate. Parallel output bus traces should be length-matched and series-terminated near the ADC to limit digital switching noise coupling back into the analog input. Decouple VDD with both a 0.1 uF ceramic and a 10 uF bulk capacitor placed within 5 mm of the supply pin. This page consolidates distributor pricing, same-family MaxLinear/Exar drop-in alternatives, and practical design notes not collected in the original manufacturer datasheet, giving engineers a single reference for procurement, second-source planning, and PCB bring-up.
XRD87L99AIQ-F - 10-Bit 2 MSPS 8-Ch MUX ADC | MaxLinear
The MaxLinear XRD87L99AIQ-F is a low-power 10-bit analog-to-digital converter with an 8-channel analog input multiplexer and a 2 MSPS sampling rate, housed in a 44-pin QFP package. It operates from a single 2.7V to 5.5V supply, draws only 24 mW typical at full speed, and falls to 0.1 mW in its hardware power-down mode. The device requires no external sample-and-hold for input signals below 100 kHz or for CCD-style signals, simplifying analog front-end design. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages into a parallel digital word at a defined clock rate. ADCs sit within the broader hierarchy of data acquisition ICs -> data converters -> mixed-signal ICs -> integrated circuits, and they are the critical bridge between analog sensors and digital processors. Multi-channel, low-power ADCs like the XRD87L99AIQ-F are typically used to digitize several sensors with one converter, reducing board area, BOM cost, and software overhead in embedded designs. Key features of the XRD87L99AIQ-F include 10-bit resolution, an integrated 8-to-1 analog multiplexer with channel-address latches, a parallel microprocessor-compatible digital interface, an external reference input, and a hardware power-down pin. Its wide input range covers GND to VDD, which lets the device directly digitize rail-to-rail sensor outputs. The 44-QFP package is industry-standard and supports conventional surface-mount assembly. Typical applications for the XRD87L99AIQ-F include multi-channel data acquisition systems, CCD signal processing chains in scanner and copier subsystems, portable and battery-powered instrumentation, industrial process monitoring, and embedded control boards that need to read several analog sensors at moderate speeds. In each case the device's low power dissipation, integrated mux, and parallel interface reduce both component count and software complexity. Designers should remember that the XRD87L99AIQ-F is in EOL/last-time-buy status according to distributor lifecycle fields, so long-life designs should plan for a qualified replacement or place a last-time-buy order. Drive the analog inputs with low-impedance sources to keep the input settling error inside the 10-bit budget, and place the 0.1uF VDD decoupling capacitor within a few millimeters of the supply pin.