FPGA и CPLD
Товары (6666)
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
The Altera (Intel) EPM7128ATC100-10 is a high-performance 3.3V EEPROM-based Complex Programmable Logic Device (CPLD) from the second-generation MAX 7000A family, built on the Multiple Array MatriX (MAX) architecture. The device delivers 128 macrocells across 4 Logic Array Blocks, supports 68 user I/O pins, and provides 4.5 ns pin-to-pin logic delays with internal counter frequencies up to 227.3 MHz, all in a 100-pin TQFP package. A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EEPROM-backed programmable logic IC that combines the instant-on behavior of a PAL/GAL with the integration density of an FPGA. CPLDs sit between discrete glue logic and larger FPGAs in the programmable logic hierarchy, providing deterministic, fast propagation delays (typically under 10 ns) and high pin-to-pin timing predictability for bus-interface, address-decode, and state-machine tasks. The MAX 7000A family is one of Altera's most widely deployed 3.3V CPLD families. Per the manufacturer datasheet, the EPM7128ATC100-10 supports 3.3V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, eliminating the need for a separate programmer. Its MultiVolt I/O interface lets the 3.3V core drive 5.0V, 3.3V, and 2.5V logic levels, allowing direct interfacing with legacy 5V peripherals, modern 3.3V ASICs, and lower-voltage LVCMOS devices on the same board. Architecturally, the device integrates 2.5K usable gates, 128 macrocells, a programmable interconnect array (PIA), and four LABs. Each macrocell contains a programmable AND/OR/registered-logic array plus a flip-flop, supporting combinatorial or registered outputs with configurable polarity. The 100-pin TQFP package (designator "TC100") is one of several package options offered across the MAX 7000A family. Typical applications include PCI bus interface glue logic, address decoding for microprocessors, state-machine and sequencer controllers, peripheral bus adapters, and legacy 5V-to-3.3V level shifting in industrial control, telecom, and embedded computing systems. When designing, ensure that ISP/JTAG signals (TCK, TMS, TDI, TDO) are routed cleanly and that unused I/O pins are configured as outputs or tri-stated to minimize in-rush current at power-up. This page synthesizes verified distributor pricing, drop-in alternative MPNs (same package, same macrocell count), application circuits, and practical design notes drawn from the manufacturer datasheet and reference designs.
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
The Intel (formerly Altera) EPM7128ATC100-7F is a high-performance 3.3V EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000A family, offering 128 macrocells, 8 Logic Array Blocks (LABs), and 100 user I/O pins in a 100-pin TQFP package. It delivers a 7.5 ns pin-to-pin propagation delay and a maximum internal operating frequency of 116.3 MHz, targeting glue-logic, bus-interface, and state-machine applications that need non-volatile, in-system programmable logic. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple SPLDs/GALs and higher-density FPGAs in the programmable logic hierarchy: SPLD < CPLD < FPGA. MAX 7000A devices use second-generation Multiple Array MatriX (MAX) architecture with each LAB containing 16 macrocells, and provide instant-on (zero-power) EEPROM configuration cells, JTAG-based IEEE Std 1149.1 boundary-scan testing, and 3.3V in-system programmability (ISP) through the built-in JTAG interface. Compared with SRAM-based FPGAs, a CPLD boots in microseconds without an external boot PROM, making it ideal for deterministic power-on logic and bus arbitration. Key features of the EPM7128ATC100-7F include 2.5K usable gates, 128 macrocells, 100 user I/O pins, a 7.5 ns tPD with 116.3 MHz fMAX, 3.0V-3.6V core supply with 2.5V/3.3V multi-voltage I/O support, JTAG IEEE 1149.1 boundary-scan, in-system programmability through JTAG, and four user-defined I/O banks with MultiVolt I/O interfacing. The 100-TQFP (14x14 mm) package is suitable for industrial-temperature (-40C to +85C) designs. The architecture combines a programmable interconnect array with 16-macrocell LABs, an EEPROM configuration memory, and a JTAG controller; each macrocell contains a programmable AND/OR array, a flip-flop, and product-term allocation logic for combinational or registered logic synthesis. MultiVolt I/O pins tolerate mixed 1.8V/2.5V/3.3V/5V interfaces, allowing direct connection to legacy 5V devices through a simple series resistor or level translator. Typical applications include PCI/ISA bus interface glue logic, address decoding and chip-select generation, state-machine and sequencer controllers, power-sequencing logic, asynchronous interface bridging (UART, I2C, SPI), legacy 5V-to-3.3V bus translation, and industrial control glue logic. The deterministic 7.5 ns propagation delay is well suited to decode-driven control paths where timing margins must be guaranteed at first silicon. When designing with this device, plan for a 3.3V core supply (3.0V-3.6V) and a JTAG chain (TCK/TMS/TDI/TDO plus optional TRST) for ISP. Confirm Quartus MAX+PLUS II support for legacy MAX 7000A bitstreams before migrating from older MAX+PLUS toolchains, and reserve four pins for JTAG if boundary-scan is required in production test.
EPM7128ATC144-10 - 128-Macrocell MAX 7000A CPLD | Intel / Altera
The Intel (formerly Altera) EPM7128ATC144-10 is a high-performance, 3.3 V EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000A family, delivering 128 macrocells, 4 Logic Array Blocks (LABs), and 68 user I/O pins in a 144-pin TQFP package. It achieves 10 ns pin-to-pin logic delays with counter frequencies up to 98 MHz, providing deterministic timing for glue-logic, bus-interface, and state-machine replacement tasks in industrial and legacy designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that combines the instant-on, deterministic timing of PAL/GAL architecture with the density and flexibility of multiple logic blocks interconnected through a programmable switch matrix. Positioned in the programmable logic hierarchy, CPLDs sit between simple SPLDs (PALs/GALs) and high-density FPGAs; they are typically chosen over FPGAs when design size is modest but deterministic propagation delay, multi-voltage I/O compatibility, and in-system programmability (ISP) through the IEEE 1149.1 JTAG interface are required. Key features include 3.3 V core supply with MultiVolt I/O supporting 5.0 V, 3.3 V, and 2.5 V logic levels, in-system programmability via the built-in JTAG (IEEE Std 1149.1) Joint Test Action Group (JTAG) interface, and on-chip EEPROM configuration memory that eliminates the need for external boot PROMs. The device operates across the commercial 0C to 70C temperature range, is housed in a 144-pin Thin Quad Flat Pack (TQFP) measuring 20 x 20 mm, and offers four user I/O banks for mixed-voltage interfacing. Architecturally, the MAX 7000A uses a second-generation Multiple Array Matrix (MAX) architecture that combines fine-grained logic elements with a continuous interconnect backbone, providing predictable timing closure independent of design placement. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable product-term steering, allowing efficient implementation of wide combinatorial and registered logic. Typical applications include bus-interface bridging (e.g., PCI-to-ISA glue logic), address decoding and wait-state generation in legacy microprocessors, peripheral chip-select generation, LED and LCD scan controllers, and I/O expansion in 5 V/3.3 V mixed-voltage systems. It is also widely used as a pin-compatible replacement for aging discrete TTL/CMOS glue logic. When designing with this device, ensure that the JTAG chain (TCK, TMS, TDI, TDO) is properly terminated and that unused I/O pins are configured as outputs or tri-stated per datasheet recommendations to minimize supply noise. ByteBlaster or USB-Blaster download cables are supported for ISP through the JTAG pins. The 144-pin TQFP footprint is shared across the MAX 7000A family, simplifying migration to higher- or lower-density siblings such as EPM7064A or EPM7256A.
EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A
The Altera (Intel) EPM7128ATI100-10 is a high-performance 3.3V EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000A family, providing 128 macrocells, 4 Logic Array Blocks (LABs), and 68 user I/O pins in a 100-pin TQFP (14x14 mm) package. The device offers a pin-to-pin propagation delay of 10 ns and a maximum toggle frequency of approximately 87 MHz, making it suitable for high-speed glue-logic, bus-interface, and state-machine designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocells with a central interconnect matrix, providing deterministic timing, instant-on operation, and high fan-in. Within the broader taxonomy, a CPLD sits between simple SPLDs (PALs/GALs) and FPGAs: it offers more logic capacity and I/O than an SPLD but lower logic density, lower power, and simpler timing closure than an FPGA. The MAX 7000A series belongs to the EEPROM-based CPLD class, which permits in-system programmability (ISP) via IEEE Std. 1149.1 JTAG and retains configuration without an external boot PROM. Key features of the EPM7128ATI100-10 include 2,500 usable gates, a 3.0V to 3.6V single-supply operation, an internal supply voltage of 3.3V, four dedicated inputs used as global clock/clear/Output-Enable controls, and an in-system programmable EEPROM configuration cell. The device supports MultiVolt I/O allowing interface to 2.5V, 3.3V, and 5.0V systems, and includes built-in JTAG boundary-scan test support. Industrial operating temperature grade (-40C to +85C) is indicated by the 'I' suffix in the part number. Architecturally, the MAX 7000A uses a second-generation Multiple Array Matrix (MAX) architecture with an enhanced interconnect scheme that reduces signal skew and improves timing predictability. Each LAB contains 16 macrocells sharing a common product-term array, and the programmable interconnect array (PIA) routes any LAB output to any other LAB input, giving designers full routing flexibility. The CMOS EEPROM process provides zero standby power for the configuration memory and supports 100 program/erase cycles. Typical applications include bus-interface bridging (e.g., 8-bit/16-bit microprocessor to peripheral glue logic), address decoding, state-machine controllers, synchronous/ asynchronous FIFO control, peripheral reconfiguration in telecom/networking line cards, industrial control logic, and as a low-cost pin-compatible replacement for legacy 5V MAX 7000 designs where 3.3V operation is acceptable. The 100-pin TQFP footprint is widely supported and offers generous I/O for bus and glue-logic applications. When designing with this part, observe the recommended decoupling scheme (one 0.1 uF plus one 10 uF bulk per supply pin) and route JTAG signals (TCK, TMS, TDI, TDO, TRST) with short, parallel traces to maintain signal integrity. Programming voltage is generated internally; no external 12V VPP is required. For new designs, verify the latest Altera/Intel Quartus support status before committing, as legacy MAX 7000A devices are supported primarily for in-system updates to existing products. This page synthesizes distributor pricing, a verified same-brand drop-in alternative matrix from the MAX 7000A family, and practical design notes not consolidated in the manufacturer datasheet.
EPM7128BTC100-10 - MAX 7000B CPLD, 128 Macrocells, 10ns | Intel
The Intel EPM7128BTC100-10 is a high-density, non-volatile CPLD from the MAX 7000B family, featuring 128 macrocells, 2.5K usable gates, and 84 user I/Os housed in a 100-pin TQFP package. It operates from a core voltage of 2.5V with a 10ns pin-to-pin delay, providing in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface and a dedicated 4-pin JTAG chain. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between small glue-logic PALs/GALs and larger FPGAs in the programmable logic hierarchy. It uses a classic EEPROM/Flash-based architecture with continuous, deterministic routing that delivers predictable timing regardless of logic placement. Compared with SRAM-based FPGAs, CPLDs boot instantly without an external configuration flash and retain configuration through power cycles, making them ideal for bus-interface bridging, power-sequencing, and control-plane glue logic. The EPM7128BTC100-10 provides 128 macrocells grouped into 8 Logic Array Blocks (LABs) of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and product-term sharing for efficient state-machine implementation. The I/O structure is 3.3V-tolerant with 5V tolerant inputs (multiVolt interface), enabling direct interfacing with 3.3V, 2.5V, and 5V mixed-voltage systems. Programmable interconnect uses the FastTrack continuous routing matrix to deliver consistent 10ns tPD and 125 MHz fCNT performance. Typical applications include bus-interface bridging, peripheral I/O expansion, address decoding for microprocessors, state-machine control, and power-supply sequencing. The 100-pin TQFP footprint is widely used in legacy industrial and telecom designs that require deterministic timing without an external configuration PROM. When designing with this device, ensure that the JTAG chain is properly terminated with TCK pull-down and TMS pull-up resistors per IEEE 1149.1. For 5V input tolerance on the user I/O banks, keep VCCIO at 3.3V while VCCINT runs at 2.5V, and observe the maximum I/O current limit of 25 mA per pin when driving LED or relay loads. This page synthesizes distributor pricing, drop-in MAX 7000B family alternatives, and practical JTAG/ISP design notes not found in the manufacturer datasheet alone.
EPM7128BTC144-7 - 128-Macro MAX 7000B CPLD, 144-TQFP | Intel
The Intel (formerly Altera) EPM7128BTC144-7 is a 128-macro-cell CMOS EEPROM-based CPLD from the MAX 7000B family, packaged in a 144-pin TQFP. It operates on a 2.5 V core supply and provides approximately 2,500 usable gates with pin-to-pin delays as fast as 7.5 ns and counter frequencies up to 126.6 MHz. The part combines high-density programmable logic with in-system programmability via the IEEE 1149.1 JTAG interface, supporting glue-logic, bus-interface, state-machine, and address-decoding roles in industrial and communications systems. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device positioned between discrete PAL/GAL devices and larger FPGAs. The MAX 7000B series is built on Altera's second-generation MAX architecture, which uses an enhanced connective array of fast, uniform interconnect channels routed to Logic Array Blocks (LABs) of 16 macro cells each. CPLDs retain their configuration in on-chip EEPROM, so they power up instantly without external boot memory - a key reason they remain popular for control-plane logic and deterministic timing paths. Key features of the EPM7128BTC144-7 include 128 macro cells, 100 user I/O pins (per the 144-pin TQFP package option), a pin-to-pin delay of 7.5 ns, an internal global clock network with up to 6 dedicated inputs, and per-macro-cell configurable clear, preset, clock-enable, and OE controls. The device supports IEEE 1149.1 boundary-scan test, multiVolt I/O interfacing (5.0 V, 3.3 V, 2.5 V mixed-voltage systems), and a JTAG-based ISP flow that lets the board be re-programmed without removing the part. The 144-TQFP footprint provides ample ground and power pins for noise-sensitive designs. The MAX 7000B architecture combines an EEPROM-backed configuration memory with a continuous FastTrack interconnect that links every LAB to every I/O pin through row and column channels. Each macro cell contains a programmable AND/OR/registered array plus an output cell with slew-rate, open-drain, and tri-state controls. This uniform fabric gives consistent timing across the device - making the EPM7128BTC144-7 well-suited to deterministic, latency-bounded applications such as bus arbitration, address decoding, and asynchronous interface bridging where FPGAs add unnecessary cost and boot complexity. Typical applications include bus-interface glue logic between microcontrollers and peripherals, address decoding in 8/16/32-bit embedded systems, state-machine controllers in industrial automation, peripheral expansion for legacy I/O ports, and pin-level logic translation between mixed-voltage buses. Designers frequently pair the part with microcontrollers such as the 8051, ARM7, or Cortex-M0 families to offload real-time decode and protocol-conversion tasks. When designing with this CPLD, place decoupling capacitors on every VCC/GND pair near the package and ensure JTAG TCK does not exceed 10 MHz for reliable ISP. The 144-TQFP package has moderate thermal dissipation; however, since the MAX 7000B core draws very low quiescent current, no heatsink is normally required. Pay close attention to the I/O bank VCCIO voltage to match the logic levels of the surrounding system. This page synthesizes distributor inventory, parametric comparisons, and practical design notes that go beyond the manufacturer datasheet - consolidating the engineering reference information a board designer needs to select, source, and implement the EPM7128BTC144-7 reliably.
EPM7128ELC84-10 - 128-Macrocell CPLD, 10ns, 5V, 84-PLCC | Intel
The Intel EPM7128ELC84-10 is a 128-macrocell, 5V, in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 7000 family, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. The device delivers 10ns pin-to-pin logic delay, 68 user I/Os, and is fabricated on an EEPROM-based CMOS process that provides non-volatile, instant-on configuration with zero standby power. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between discrete glue logic and FPGAs in the digital design hierarchy: it provides deterministic, single-clock-cycle propagation delays, instant-on behavior from on-chip EEPROM, and abundant wide-decoding capability, while being simpler and lower-cost than an FPGA. CPLDs are widely used as the "glue logic" tier of a digital system, bridging processors, memories, and peripherals. The MAX 7000 family is a classic EE CPLD architecture organized as Logic Array Blocks (LABs) with a programmable interconnect array (PIA). Key features of the EPM7128ELC84-10 include 128 macrocells (equivalent to roughly 2500 usable gates), 68 user I/O pins, 12 dedicated input pins, 5V core and I/O operation (the "E" suffix indicates the enhanced 5V family), and 10ns combinatorial propagation delay through the PIA. Per-pin I/O standards include TTL and CMOS, and the device supports in-system programmability (ISP) via the IEEE 1149.1 JTAG interface, plus a 3.3V or 5V programming voltage selection on dedicated pins. Technically, the MAX 7000 architecture provides predictable timing and high pin-to-pin performance, making it ideal for address decoding, bus interfacing, state-machine control, and asynchronous logic consolidation. Its non-volatile EEPROM cells eliminate the boot PROM required by SRAM FPGAs and remove the need to reload configuration at power-up, a feature that materially simplifies board design. Typical applications include system-level address decoding for memory and peripherals in 8/16/32-bit microcontroller and microprocessor designs, bus-interface bridging (e.g., 8-bit to 16-bit width translation), state-machine-based I/O control, and legacy industrial glue-logic replacement. The wide 5V tolerance makes it particularly suited to retrofits of legacy 5V systems. When designing with this part, note that 5V-tolerant I/Os are increasingly rare in newer CPLD/FPGA families; confirm that downstream devices accept 5V inputs before mixing. Also note the 84-pin PLCC is a through-hole-style J-lead socket-compatible package - verify that your board design accommodates a socket or PLCC footprint. The "10" suffix denotes the commercial speed grade (10ns tPD); a "-15" or "-7" grade variant exists if different timing is required. This page synthesizes distributor stock and pricing, drop-in same-package alternatives, and practical design notes not found in the bare datasheet, helping engineers make a confident, source-cited sourcing decision.
EPM7128ELC84-12 - 128-Macrocell MAX 7000 CPLD, 12ns, 84-PLCC
The Altera (now Intel) EPM7128ELC84-12 is a member of the classic MAX 7000 family of Complex Programmable Logic Devices (CPLDs), delivering 2,500 usable gates, 128 macrocells, and 84 user I/Os in a 5V, 84-pin Plastic Leaded Chip Carrier (PLCC) package. Per the verified distributor data, the device carries the "-12" speed grade with a maximum propagation delay of 12 ns (tpd1) and an internal global clock frequency up to 90.9 MHz (per GlobalSpec listing). The CMOS, EEPROM-based architecture provides non-volatile, in-system programmable logic with instant-on behavior and 100% generic interconnect, making it a proven choice for glue-logic, bus-interface, and state-machine replacement. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the deterministic timing of PAL/GAL architectures with the density of small FPGAs. It belongs to the broader hierarchy of programmable logic devices (PLDs), sitting between simple PLDs (PALs/GALs) and high-density FPGAs. CPLDs are characterized by non-volatile configuration (typically EEPROM or flash), predictable pin-to-pin timing (fixed tpd), and low power consumption, making them ideal for control-plane and interface logic in mixed-signal systems. Key features include 128 macrocells organized into 8 Logic Array Blocks (LABs) of 16 macrocells each, 100% connectivity with a uniform interconnect, programmable interconnect array (PIA), and a JTAG-compliant IEEE 1149.1 boundary-scan interface for in-system programming (ISP). The device operates from a single 5V supply (4.75V to 5.25V), supports commercial-grade 0C to +70C operation, and offers 12 ns pin-to-pin logic delay with 4.5 ns setup time, suitable for moderate-speed control and interface tasks. The MAX 7000E architecture uses a classic EEPROM cell plus CMOS look-up table (LUT) implementation per macrocell, with each macrocell containing a programmable AND/OR array, a flip-flop, and a tri-state output buffer. The PIA routes any LAB output to any other LAB input, eliminating routing congestion. Compared to the original MAX 7000S family, the E variant adds enhanced features such as faster ISP and additional global clock options, while retaining the same JTAG and pinout architecture. Typical applications include peripheral bus interfacing (ISA, PCI target, VME), address decoding and chip-select generation, state-machine replacement, glue logic between microprocessors and peripherals, and legacy industrial control retrofits. The 84-pin PLCC package is also socket-friendly, simplifying prototyping and field replacement. When designing with the EPM7128ELC84-12, plan for the 12 ns propagation delay when targeting synchronous buses above 50 MHz; the part is rated for 5V I/O only and is not 5V-tolerant at 3.3V rails - level translation is required when interfacing to 3.3V logic. Use the JTAG ISP chain (TCK/TMS/TDO/TDI) plus Quartus II or MAX+PLUS II for in-system programming and logic synthesis. This page synthesizes distributor pricing, verified MAX 7000E family alternatives, and practical 5V CPLD design notes not found in the manufacturer datasheet alone.
EPM7128ELC84-20 - MAX 7000 CPLD, 128MC, 20ns, 5V, PLCC-84 | Altera
The Altera (now Intel) EPM7128ELC84-20 is a high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000 family, providing 128 macro cells, 2,500 usable gates, and 68 user I/O pins in a surface-mount 84-pin PLCC (Plastic Leaded Chip Carrier, J-Lead) package with a 20 ns pin-to-pin logic delay. What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs (such as PALs and GALs) and FPGAs in the programmable logic hierarchy. CPLDs are characterized by instant-on (no configuration load time), deterministic timing, and low power consumption, making them ideal for glue-logic, bus interfacing, and state-machine tasks. The MAX 7000 family is based on Altera's second-generation MAX architecture and supports 100% TTL emulation while integrating SSI, MSI, and LSI logic functions on a single device. Key features of the EPM7128ELC84-20 include 5V core operation, 2500 typical gates (the -20 speed grade corresponds to a 20 ns tPD and approximately 125 MHz in-system performance), in-system programmability via the IEEE Std. 1149.1 (JTAG) interface, and four pin-compatible speed grades (-5, -7, -10, -12, -15, -20) that allow designers to migrate between speed and power trade-offs without PCB rework. The device is fabricated on an EEPROM-based process, providing non-volatile storage of the configuration so the part powers up instantly programmed. Architecturally, the EPM7128ELC84-20 implements the Logic Array Blocks (LABs) connected through the Programmable Interconnect Array (PIA). Each macro cell contains a programmable AND/OR array with a flip-flop, shareable expanders, and a configurable I/O architecture supporting 3.3V or 5V interface levels. The 84-pin PLCC (J-Lead) package has a JEDEC MS-018 footprint and supports 68 user I/O with 4 dedicated inputs (GCLK, OE2/GCLK2, OE1, CLR) plus TDI, TDO, TMS, TCK for JTAG. Typical applications include address decoding and bus-interface glue logic in 5V microprocessor systems, peripheral control in industrial automation, I/O expansion and signal conditioning in legacy telecom equipment, and prototyping platforms that benefit from instant-on programmable logic. Compared to FPGAs, the MAX 7000 family excels at deterministic combinatorial paths and is widely used in PC/104, ISA, and 8051-family bus arbiter designs. When designing with this part, note that the PLCC-84 J-Lead package requires a through-hole or socket footprint, which makes field replacement easy. Designers should follow Altera's MAX 7000 family datasheet guidelines for power decoupling (typically 0.1 uF + 10 uF bulk near VCC pins) and unused-pin termination (tie unused I/Os to VCC or GND through 10 kohm to minimize quiescent current). This page synthesizes distributor pricing, drop-in 5V same-package alternatives within the MAX 7000 family, and practical design notes not found in the manufacturer datasheet.
EPM7128ELI84-20 - 128-Macrocell CPLD, 20ns, 84-PLCC | Intel / Altera
The Intel (formerly Altera) EPM7128ELI84-20 is a 128-macrocell Classic MAX 7000 CPLD with 20ns pin-to-pin delay, 2.5K usable gates, 68 user I/Os, and 5V operation, housed in an 84-pin plastic J-leaded chip carrier (PLCC). Built on a 0.18 µm (note: MAX 7000B/E family uses a 0.18 µm equivalent EEPROM process) EEPROM-based CMOS architecture, the device delivers non-volatile in-system programmability via the IEEE 1149.1 JTAG interface and supports ISP through the MAX+PLUS II or Quartus II design environments. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell arrays on a single die, providing deterministic, near-zero-latency combinational and registered logic for glue-logic, bus-interface, and state-machine tasks. Within the broader taxonomy, CPLDs sit between simple PLDs (PAL/GAL) and high-density FPGAs, offering instant-on, single-chip solutions for low-to-medium logic density (typically 32 to 512 macrocells) without external boot memory. Key features include 128 macrocells distributed across 8 logic array blocks (LABs), a maximum operating frequency of approximately 62.5 MHz (fCNT), 2500 usable gates, 4.5 to 5.5V VCC core supply, and an industrial operating temperature range of -40 °C to +85 °C. The 84-pin PLCC package offers J-leads suitable for socketed through-hole mounting, easing prototype rework and field upgrades. Each I/O pin has individually programmable slew rate, open-drain, and registered/combinational configuration options. Architecturally, the MAX 7000 family uses a programmable interconnect array (PIA) that routes all LAB signals globally, ensuring predictable, fixed-delay timing regardless of placement. The macrocell includes a programmable AND/OR array feeding a configurable flip-flop, allowing combinational, registered, latched, or tri-state output functions. In-system programming (ISP) allows field firmware updates without removing the device from the board. Typical applications include legacy bus-interface bridging (e.g., 8/16-bit µC bus expansion), address decoding and glue logic, power-sequencing state machines, peripheral multiplexing for microcontrollers, and industrial control systems. The EPM7128ELI84-20 is particularly common in telecom backplane designs and ISA/PCI bridge logic where deterministic 20ns timing and 5V tolerance matter. When designing with this part, ensure the VCCIO supply matches the driven logic-level thresholds and respect the global clear (GCLRn) and output-enable (OE) pin polarity for active-low control. For new designs, prefer the MAX II or MAX V family for lower power, but choose EPM7128ELI84-20 when 5V tolerance, socketed PLCC form factor, or pin-compatible legacy replacement are required. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet — including a verified pinout, drop-in cross-reference, and a comparison table against same-package Altera/Intel MAX 7000B family members.
EPM7128EQC100-10 - 128-Macrocell MAX 7000 CPLD, 10ns, PQFP-100
The Altera (now Intel) EPM7128EQC100-10 is a high-performance, EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, offering 128 macrocells, 2,500 usable gates, and 84 user I/O pins in a 100-pin Plastic Quad Flat Pack (PQFP-100) package with a 10 ns pin-to-pin propagation delay. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that combines multiple PAL-like macrocell arrays interconnected by a programmable interconnect matrix. CPLDs sit in the broader hierarchy of programmable logic devices (CPLD -> PLD -> programmable logic -> digital semiconductor), offering deterministic timing, low power, and glue-logic integration that historically replaced dozens of 74-series TTL parts on a single chip. Key features include a 100 MHz internal performance, 5.0 V CMOS core technology with 4.75 V to 5.25 V supply range, in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, and a commercial 0 °C to 90 °C operating temperature range. The device is built on a second-generation MAX architecture with four Logic Array Blocks (LABs) and a global interconnect that delivers fixed, predictable propagation delays regardless of routing. The EPM7128EQC100-10 architecture combines 128 macrocells grouped into four LABs of 16 macrocells each, with a Programmable Interconnect Array (PIA) that routes signals globally. Each macrocell contains a programmable AND/OR array plus a configurable flip-flop, supporting both combinational and registered logic with deterministic 10 ns tpd and 100 MHz fCNT performance. Typical applications include bus interface bridging (e.g., 8-bit/16-bit microcontroller glue logic), address decoding and chip-select generation in embedded systems, peripheral control and timer/counter replacement, and legacy 74-series TTL integration. The MAX 7000 family is widely used in industrial controllers, telecommunications line cards, and test equipment where instant-on non-volatile configuration and deterministic timing are required. When designing with this part, ensure the JTAG chain respects the TCK-to-TDI/TDO timing specified in the MAX 7000 datasheet family, and provide a clean 5 V supply with adequate bulk decoupling. Note that this part is now in Intel's legacy portfolio and lifecycle should be confirmed before new designs. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 7000 family, and practical design notes not found in the manufacturer datasheet alone - useful for engineers maintaining legacy hardware or sourcing hard-to-find programmable logic.
EPM7128EQC100-20 - MAX 7000 CPLD, 128 Macrocells, 84 I/O | Altera
The Altera (Intel) EPM7128EQC100-20 is a high-density CMOS EPLD (Erasable Programmable Logic Device) from the MAX 7000 family, offering 2.5K usable gates, 128 macrocells and 84 user I/O pins in a 100-pin PQFP (Plastic Quad Flat Pack) package. The "-20" speed grade denotes a pin-to-pin propagation delay of 20 ns and an internal counter frequency capability tied to the device's tpd1/tpd2 specifications, making it well suited to glue-logic and bus-interface designs that have been in production since the mid-1990s. An EPLD (Erasable Programmable Logic Device) is a non-volatile, electrically erasable CMOS logic device that sits hierarchically between PAL/GAL simple PLDs and full FPGAs. Within the MAX 7000 architecture, logic is organized into Logic Array Blocks (LABs), each containing 16 macrocells with a programmable AND/OR array, a product-term allocator, and a configurable flip-flop. A global Interconnect Array (PIA) routes signals between LABs and the I/O pins, and a JTAG-compliant IEEE 1149.1 boundary-scan interface is provided for in-system programming (ISP) and board-level testing. Key features of the EPM7128EQC100-20 include 128 macrocells, 250 MHz maximum internal frequency, 4.5 ns propagation delay (per third-party digchip datasheet summary), CMOS 5V I/O with 3.3V/5V tolerant interfacing, in-system programmability via JTAG, and a commercial operating temperature grade of 0°C to 90°C. The 100-pin PQFP package supports 84 user I/Os while providing dedicated JTAG, clock, clear and global OE pins, making it suitable for legacy parallel-bus interfaces, address decoding, and peripheral control logic. Typical applications include industrial control boards, telecommunications glue logic, address decoding and bus interfacing for legacy microprocessors, peripheral controllers, and pin-compatible upgrades for older MAX 7000 designs. With 128 macrocells the device can absorb the equivalent of roughly 200 to 400 standard 22V10-style PAL equations in a single chip, simplifying board BOMs and reducing chip count in mature designs. When designing with this part, engineers should note that the 5V core supply, commercial temperature grade and PQFP footprint are characteristic of 1990s-era designs. Modern 3.3V-only or low-power designs should consider MAX II, MAX V or MAX 10 CPLDs as alternatives, as the EPM7128EQC100-20 is now typically sourced for maintenance, repair and legacy production rather than new designs. Designers must observe the 20 ns timing budget carefully for high-speed bus interfaces such as ISA or PCI. This page synthesizes distributor pricing, drop-in same-package alternatives (EPM7128EQC100-10, EPM7128SQC100-7, EPM7128STC100-10), pinout data and practical design notes not assembled in any single manufacturer document.
EPM7128EQI100-15 - MAX 7000 CPLD, 128 Macrocells, 15ns | Altera/Intel
The Altera (now Intel) EPM7128EQI100-15 is a member of the MAX 7000 family of Complex Programmable Logic Devices (CPLDs), delivering 128 macrocells, 2.5K usable gates, and a 15 ns pin-to-pin propagation delay in a 100-pin PQFP package. The device operates from a 5 V supply and provides 84 user I/O pins, making it suitable for glue-logic, bus interfacing, and state-machine replacement tasks in industrial and telecom designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single die with a centralized interconnect fabric. CPLDs sit in the hierarchy between simple SPLDs and larger FPGAs, offering deterministic, fast pin-to-pin timing with instant-on behavior because configuration is stored in on-chip EEPROM rather than SRAM. The MAX 7000 family uses an EEPROM-based architecture, which means the device retains its programmed logic across power cycles without an external boot PROM, a notable advantage over SRAM-based FPGAs in cost-sensitive and safety-critical designs. Key features of the EPM7128EQI100-15 include 128 macrocells organized as 8 logic array blocks (LABs) of 16 macrocells each, a maximum operating frequency of approximately 76.9 MHz, programmable macrocell flip-flops, and a JTAG-compliant IEEE 1149.1 boundary-scan test interface. The "I" suffix in the part number denotes the industrial temperature grade of -40 °C to +85 °C, while the "E" designates the enhanced MAX 7000E variant. Each macrocell supports configurable clear, preset, clock, and output enable signals, allowing designers to implement combinatorial and registered logic in the same device. Typical applications include bus decoding and address mapping in microprocessor systems, I/O expansion for legacy ASICs, glue logic between modern processors and peripherals, board-level control sequencers, and small state-machine implementations. The 15 ns propagation delay comfortably supports standard 33 MHz PCI bus cycles and most asynchronous logic interfaces in industrial control hardware. When designing with this part, note that the EEPROM programming cycles are rated in the thousands, so the device is intended for prototyping or in-system updates rather than field-reprogrammable applications. Designers should also observe the 5 V VCC requirement and ensure decoupling complies with the Altera reference design to avoid noise-induced logic errors. This page synthesizes distributor pricing, drop-in speed-grade and temperature-grade alternatives, and engineering notes not found in the bare datasheet, providing a single source for engineers selecting a 5 V MAX 7000 CPLD for production builds.
EPM7128SLC84-10 - 128-Macrocell MAX 7000 CPLD | Intel
The Intel (formerly Altera) EPM7128SLC84-10 is a high-density, high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, housed in an 84-pin PLCC (J-lead) package. The device provides 128 macrocells, 2500 usable gates, and 68 user I/O pins, with a 10 ns pin-to-pin logic delay through the interconnect array. The 'S' suffix denotes in-system programmability via a built-in IEEE Std. 1149.1 JTAG interface plus 5.0V-tolerant I/O with MultiVolt support. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip, connected through a central programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy between discrete PALs/GALs and larger FPGAs: they offer deterministic timing (typically predictable propagation delays), instant-on configuration from on-chip EEPROM, and moderate logic densities (hundreds of macrocells vs. millions of LUTs in modern FPGAs). The MAX 7000 family was Altera's second-generation MAX architecture and became the de-facto standard for glue-logic integration, bus interfacing, and state-machine consolidation in industrial and telecom designs from the mid-1990s through the 2000s. Key specifications include 128 macrocells (each containing a programmable AND/OR array plus one flip-flop), a maximum operating frequency of approximately 125 MHz for counter operation, a tPD (pin-to-pin delay) of 10 ns, and a tSU (setup time) of 7 ns. The device operates from a single 5.0 V supply (VCCINT = 4.75-5.25 V) with MultiVolt I/O supporting 2.5 V, 3.3 V, or 5.0 V mixed-voltage interfacing. The 84-pin PLCC package exposes 68 usable I/O plus JTAG and configuration pins. Internally, the MAX 7000S architecture uses four Logic Array Blocks (LABs) interconnected by a continuous programmable interconnect array (PIA). Each LAB contains 16 macrocells; each macrocell combines a programmable AND array, an OR/Exclusive-OR gate, a programmable flip-flop, and selectable clear/preset/clock control. Programming data is stored in on-chip EEPROM cells, allowing the device to retain its configuration indefinitely without external memory. The -10 speed grade indicates a 10 ns propagation delay. Typical applications include bus-interface bridging (e.g., 8/16/32-bit MCU-to-peripheral glue logic), address decoding and chip-select generation, state-machine consolidation in industrial controllers, and 5 V system glue logic in legacy telecom and factory-automation equipment. The -10 grade is the slowest of the three speed grades offered in this package (-7, -10, -15) and is therefore preferred when propagation delay is not timing-critical. When designing with this part, note that 84-pin PLCC sockets are widely available but require through-hole PCB footprint - plan for socket cost and assembly labor. Designers migrating legacy 5 V designs to 3.3 V MCUs often choose the MAX 7000S as the voltage-translation bridge because of its MultiVolt pinout. This page synthesizes distributor pricing, drop-in alternatives drawn from the MAX 7000S family, and practical design notes not found in the manufacturer datasheet.
EPM7128SLC84-10 - MAX 7000 CPLD, 128 Macro, 68 I/O, 10ns | Intel
The Intel (formerly Altera) EPM7128SLC84-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 128 macrocells, 84 pins in a PLCC-84 (J-lead) package, and 68 user I/Os with a 10 ns pin-to-pin propagation delay. It is fabricated on a 5 V, EEPROM-based second-generation MAX architecture that delivers in-system programmability via the IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantaneously-on programmable logic device that bridges the gap between discrete glue logic and FPGAs. Within the broader taxonomy, the EPM7128SLC84-10 belongs to: CPLD -> PLD -> programmable logic -> digital semiconductor -> integrated circuit. It provides deterministic, fixed propagation delay across all 128 macrocells, making it ideal for glue-logic, bus interfacing, address decoding, and state-machine replacement. Unlike SRAM-based FPGAs, the EEPROM configuration cell retains the bitstream without external boot memory and powers up ready to operate. Key specifications include a maximum operating frequency of 125 MHz, 250 MHz internal frequency, 4.5 ns propagation delay (per the Alldatasheet index), and a maximum of 2500 usable gates. The device supports programmable speed/power optimization, allowing individual macrocells to run at reduced power with a small timing penalty. The 84-pin Plastic Leaded Chip Carrier (PLCC) package uses J-bend surface-mount leads suitable for socketed programming and production assembly. The MAX 7000S architecture employs a programmable interconnect array (PIA) that routes any macrocell output or I/O pin to any other macrocell input, providing full routability. Each macrocell contains a programmable AND/OR/flip-flop array with configurable clear, preset, clock, and output-enable controls. MultiVolt I/O pins permit interfacing with 2.5 V, 3.3 V, and 5 V logic without external level translation. The on-chip JTAG boundary-scan logic supports IEEE 1149.1 testing and in-system programming. Typical applications include bus interface bridging (e.g., 8/16/32-bit microprocessor glue logic), peripheral controller state machines, address decoding and chip-select generation, board-level reset sequencing, LED and seven-segment display multiplexing, and legacy industrial-control logic upgrades. Designers choose this part when deterministic timing, instant-on behavior, and single-chip simplicity outweigh the higher logic density of an FPGA. A primary design consideration is the 5 V VCC requirement; modern 3.3 V-only systems need a separate rail. JTAG chain ordering must keep TCK/TMS/TDO/TDI integrity when multiple devices share the boundary-scan bus. For new designs, verify the Altera/Intel MAX II or MAX V equivalent if lower power or 1.8 V support is required. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes drawn from the manufacturer MAX 7000 family datasheet and verified web sources.
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
The Intel / Altera EPM7128SLC84-15 is a 128-macrocell member of the classic MAX 7000S family of CMOS Complex Programmable Logic Devices (CPLDs), packaged in an 84-pin PLCC (J-Lead, J84) and rated for the -15 speed grade (tPD = 15 ns). The MAX 7000S family provides in-system programmability via IEEE Std. 1149.1 (JTAG), 5V tolerant I/O, and on-chip non-volatile EEPROM configuration memory, making the device a drop-in logic-integration solution for legacy industrial designs. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that sits between simple PAL/GAL devices and large SRAM-based FPGAs in the programmable logic hierarchy. CPLDs are typically used for glue logic, bus decoding, state-machine control, and I/O expansion because they offer deterministic timing, instant-on configuration (no boot PROM required), and predictable pin-to-pin delays across the whole device. Within that hierarchy, MAX 7000S is one of the longest-running Altera CPLD families, predating the modern MAX II / MAX V series. Key features of the EPM7128SLC84-15 include 128 macrocells (2,500 usable gates), 68 user I/Os in the 84-pin PLCC footprint, a maximum internal operating frequency of up to 76.9 MHz (the -15 speed grade supports roughly 125 MHz fMAX in commercial temperature), and 4.5 ns propagation delay per pin as reported on third-party datasheet mirrors. The device is built on a 5V-tolerant CMOS EEPROM process and supports multi-volt I/O for interfacing with 3.3V and 5V logic. Programming is performed through the built-in JTAG port using Quartus or MAX+PLUS II toolchains. Typical applications include industrial PLC and process-control glue logic, telecommunications backplane bus bridges, address decoding and wait-state generation in legacy x86 embedded systems, and ASIC-prototype logic replacement. The 84-PLCC package makes the part attractive for socketed legacy boards and field-replacement scenarios. When designing with this device, ensure that the JTAG chain is correctly ordered if multiple devices are cascaded, and observe the I/O bank's 5V VCCIO requirement when interfacing with legacy TTL logic. The instant-on EEPROM configuration is a key advantage over SRAM-based FPGAs in safety-critical systems. This page synthesizes distributor pricing, drop-in alternatives within the same MAX 7000 family, and practical design notes that are not consolidated in any single manufacturer datasheet.
EPM7128SLC84-15N - 128-Macrocell CPLD, 76.9MHz | Altera
The Altera EPM7128SLC84-15N is a 2.5K-gate MAX 7000-series complex programmable logic device with 128 macrocells, 68 I/Os, a 76.9 MHz maximum operating frequency, and a 15 ns speed grade in an 84-pin PLCC package. It operates from a 5 V supply and is designed for programmable digital control, interface, decoding, and glue-logic designs. A CPLD is a user-programmable semiconductor that combines configurable logic blocks with nonvolatile configuration memory. In the broader hierarchy, a CPLD is a programmable logic device, a semiconductor, and a complement to FPGA and mask-programmed logic solutions. The MAX 7000 architecture provides deterministic timing and straightforward integration into designs that need programmable Boolean functions, address decoding, bus control, or legacy-interface logic. Key verified features include 128 macrocells, 2.5K logic gates, 68 I/Os, 76.9 MHz operation, 5 V operation, and an 84-pin PLCC package. The LC suffix identifies the leaded-chip carrier package, while the -15 suffix identifies the 15 ns device speed grade. One distributor result describes the EPM7128SLC84-15 as functionally and pin-compatible with earlier EPM7128 variants in the same speed grade and package, making replacement selection primarily a matter of package, speed, electrical, and qualification verification. The EPM7128SLC84-15N is suitable for industrial and legacy control logic where a 5 V supply, leaded PLCC package, and a moderate logic capacity are acceptable. Typical uses include industrial automation interfaces, peripheral controllers, signal conditioning, state machines, bus arbitration, and board-level control. It can also serve as a bridge between older microprocessors and newer digital subsystems when the required logic fits within 128 macrocells. The primary design consideration is verifying timing, power, pinout, and programming compatibility against the system requirements. Because a CPLD replacement is not automatically safe merely because the family name matches, confirm the package pin count, pin assignments, I/O voltage, macrocell count, speed grade, and programming file support. The 84-pin PLCC footprint should not be treated as interchangeable with QFP, TQFP, or BGA packages. This page consolidates verified source specifications, pricing references, cross-reference results, and practical replacement guidance. It also distinguishes the exact EPM7128SLC84-15N from the separately listed EPM7128SLC84-15 and explains when a substitute can be considered for legacy 5 V MAX 7000 designs.
EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
The Intel (Altera) EPM7128SLC84-6N is a high-performance CMOS CPLD from the MAX 7000S family, delivering 2.5K system gates, 128 macro cells, and 68 user I/Os in an 84-pin PLCC (J-lead) package. Operating at 5V with a 6 ns pin-to-pin delay, this device targets glue-logic, bus-interface, and state-machine applications where deterministic timing and in-system programmability (ISP) are essential. It is built on EEPROM process technology and is fully compatible with the legacy MAX+PLUS II / Quartus toolchains for bitstream generation and JTAG-based programming. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the deterministic timing of PAL/PLA architectures with the density and macro-cell flexibility of modern FPGAs. Within the broader programmable-logic taxonomy, the CPLD sits between simple SPLDs (PALs/GALs) and high-density SRAM-based FPGAs, offering instant-on behavior (no external boot PROM required) and predictable propagation delays that simplify timing closure for control-plane logic. The MAX 7000S series is one of the industry's longest-lived CPLD families, valued for its low power consumption, 5V tolerance, and ability to absorb wide glue-logic functions into a single package. Key features of the EPM7128SLC84-6N include 128 macro cells (each containing 16 product terms), 2500 usable system gates, an fMAX of 147.1 MHz, four dedicated inputs (for high-speed clocking), two global clocks, and JTAG-compliant IEEE 1149.1 boundary-scan support. The 6 ns speed grade represents one of the fastest bins in the MAX 7128 family, making it suitable for memory-interface controllers, address decoding, and peripheral glue where sub-10 ns response is required. Typical applications include ISA/PCI bus interface logic, peripheral address decoding, microcontroller I/O expansion, state-machine-based control, and legacy 5V industrial systems. The non-volatile EEPROM cell array eliminates the need for external boot memory, supporting instant-on configuration at power-up. Designers should note that the EPM7128SLC84-6N is a legacy part approaching end-of-life for new designs; production volumes continue for maintenance, but long-term availability for new programs should be confirmed via distributor channels. Pin-compatible speed-grade variants (EPM7128SLC84-7, -10, -15) and identical-die QFP packages (EPM7128SQC100, EPM7128BTC100) exist for design flexibility. This page synthesizes drop-in alternative listings, parametric comparisons against same-family MAX 7000S variants, and practical design notes (power sequencing, ISP/JTAG usage, 5V mixed-signal considerations) that go beyond the basic datasheet summary, helping engineers sourcing, replacing, or re-spinning legacy MAX 7000S designs.
EPM7128SLC84-7N - 128 Macro Cell 7.5ns MAX 7000S CPLD | Intel
The Intel (formerly Altera) EPM7128SLC84-7N is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 128 macro cells and 2,500 usable gates in an 84-pin PLCC (J-lead) surface-mount package. The device is specified at the -7 speed grade with a maximum pin-to-pin propagation delay (tpd) of 7.5 ns and a maximum operating frequency of 125 MHz, supporting 5V core operation from a 4.75 V to 5.25 V supply rail. A Complex Programmable Logic Device (CPLD) is a non-volatile, in-system programmable logic IC that bridges the gap between discrete logic gates and full FPGAs. CPLDs use EEPROM or flash memory cells to store their configuration, retaining bitstream through power cycles without external boot memory. Architecturally, CPLDs belong to the programmable logic hierarchy (CPLD -> PLD -> programmable logic -> digital IC -> semiconductor) and are typically deployed for glue logic, bus bridging, state-machine control, and I/O expansion where deterministic timing and instant-on behavior matter more than raw logic density. Key features of the EPM7128SLC84-7N include 128 macro cells organized into 8 logic array blocks (LABs), 68 user I/O pins, in-system programmability (ISP) via JTAG, and counter speeds up to 175.4 MHz on faster speed grades. The MAX 7000S second-generation MAX architecture integrates a programmable interconnect array (PIA) that routes signals between LABs with predictable timing, eliminating the routing-variation problem of early PLDs. Built on advanced CMOS EEPROM technology, the device offers 100% TTL-compatible I/O and supports hot-socketing for legacy bus designs. Typical applications include 5V bus-interface glue logic in industrial control boards, address decoding and interrupt steering in embedded motherboards, legacy peripheral replacement for 74LS/74F TTL logic, state-machine controllers for motor drives, and I/O expansion around microcontrollers and DSPs. The wide 5V tolerance also makes it suitable for prototyping legacy PC/104 and VMEbus systems. When designing with this device, ensure that the JTAG pins (TDI, TDO, TMS, TCK) are properly terminated and that the input ramp time on VCC respects the EEPROM programming requirements. The 84-pin PLCC package requires a socket or hand-soldered footprint; for new designs consider the modern MAX II or MAX V equivalent. Power dissipation scales with the toggle rate of the programmed logic and the output loading.
EPM7128SLI84-10 - MAX 7000 CPLD 128MC 10ns 84-PLCC | Intel
The Intel (formerly Altera) EPM7128SLI84-10 is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 2.5K usable gates, 128 macro cells, and 68 user I/Os in a 84-pin Plastic Leaded Chip Carrier (PLCC) package. It operates at 100 MHz internal frequency with a 10 ns pin-to-pin propagation delay, and is built on a 5 V CMOS technology node with EEPROM-based configuration memory that is in-system programmable (ISP) via JTAG. The SLI suffix indicates the industrial operating temperature range of -40 °C to +85 °C, while the -10 speed grade denotes a 10 ns tPD. The device is organized as 8 Logic Array Blocks (LABs) of 16 macro cells each, interconnected by a programmable interconnect array (PIA) shared with the I/O control blocks. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the architectural simplicity of a PAL/GAL with the density and flexibility of an FPGA for glue-logic, bus-interface, state-machine, and control-plane tasks. In the digital-system hierarchy, CPLDs sit between discrete 74-series glue logic and full FPGAs: they offer deterministic timing, instant-on from non-volatile memory, and pin-to-pin delays of a few nanoseconds - making them ideal for deterministic control logic rather than parallel data-path processing. The MAX 7000S family specifically targets 5 V system designs and remains a long-lived platform for industrial and legacy upgrades. Key features include 128 macro cells, 68 available user I/Os, JTAG boundary-scan support compliant with IEEE Std 1149.1, multi-voltage I/O (5.0 V core with 3.3 V or 5.0 V interface), open-drain or totem-pole output options per pin, and programmable power-saving mode per macro cell. The 84-pin PLCC package provides through-hole or socket compatibility for legacy boards, while the in-system programmability via the ByteBlaster or ByteBlasterMV cable eliminates the need for a separate programmer. Typical applications include 5 V industrial control boards, ISA/PCI bus-interface glue logic, address decoding, state-machine controllers, and legacy microprocessor peripheral interfaces where deterministic 10 ns timing and instant-on from EEPROM configuration are required. When designing with this part, plan for the 5 V VCCINT requirement and consider the EPM7128SLI84-10N lead-free variant if RoHS compliance is mandatory for new designs. This page synthesizes distributor pricing, drop-in 84-PLCC alternatives, and practical design notes not found in the original Altera datasheet.
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
The Intel / Altera (formerly Altera Corporation) EPM7128SLI84-10N is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 2,500 usable gates and 128 macro cells with 68 user I/Os in a 84-pin Plastic Leaded Chip Carrier (PLCC) package. The "-10N" speed grade specifies a pin-to-pin propagation delay (tPD) of 10 ns, and the device is built on EEPROM process technology for non-volatile in-system programmability. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the instant-on, deterministic timing characteristics of PAL/GAL architecture with macro-cell granularity typically ranging from 32 to 512 cells. CPLDs sit in the programmable logic hierarchy between simple SPLDs (PAL/GAL) and larger FPGAs, and are typically used for glue logic, bus interfacing, state-machine control, and decoder functions where deterministic 5-15 ns pin-to-pin delays and high fan-in logic replacement matter more than raw register count. Key features of the EPM7128SLI84-10N include a maximum toggle frequency of 125 MHz, JTAG-compliant IEEE Std 1149.1 boundary-scan support, an I/O bank that is 5 V tolerant with 3.3 V or 5 V core operation, and four pin-compatible "-10/-12/-15/-20" speed grades in the same PLCC-84 footprint. The MAX 7000S architecture provides 100% factory-tested logic and supports MultiVolt I/O for interfacing to 2.5 V, 3.3 V, and 5 V devices on the same board. An internal 3.3 V regulator (when powered from 5 V) reduces active power by approximately 50% compared with the original MAX 7000 family. Architecturally, the device is organized as 16 Logic Array Blocks (LABs), each containing 16 macro cells, interconnected by a continuous Programmable Interconnect Array (PIA). Each macro cell contains a programmable AND/OR array, a configurable flip-flop, and per-cell product-term allocation. The EEPROM-based non-volatile configuration stores the bitstream on-chip, eliminating external boot memory and enabling instant-on behavior at power-up - a key advantage over SRAM-based FPGAs. Typical applications for the EPM7128SLI84-10N include bus-interface glue logic (PCI, ISA, VME), address decoding and chip-select generation, state-machine controllers, peripheral I/O expansion, and legacy 5 V system replacement. Designers frequently choose this part when migrating from discrete 74-series TTL or from PAL/GAL devices where higher density or in-system reprogrammability is needed. A key design consideration when using the EPM7128SLI84-10N in a new board design: modern designs targeting the PLCC-84 footprint should plan for the part's mature (last-time-buy / NRND) lifecycle status and consider pin-compatible MAX II or MAX V devices for new production. For legacy designs where PCB rework is not feasible, the EPM7128SLI84-10N remains the pin-compatible drop-in solution. Design with proper decoupling (one 0.1 uF + one 10 uF per VCC/ GND pair) and follow Altera AN 74 (MAX 7000 in-system programmability) for ISP-friendly JTAG chains. This page synthesizes distributor pricing, drop-in alternatives within the PLCC-84 footprint, and practical design notes not found in the manufacturer datasheet alone.
EPM7128SLI84-15 - 128-Macrocell CPLD, 15ns, PLCC-84 | Altera / Intel
The Altera (Intel) EPM7128SLI84-15 is a 128-macrocell EE PLD from the MAX 7000 programmable logic family, delivering 15 ns pin-to-pin propagation delay in a 84-pin PLCC (J-lead) package. It operates from a single 4.5 V to 5.5 V supply and supports configurable I/O standards at 3.3 V or 5 V, enabling mixed-voltage interfacing with both legacy TTL and modern low-voltage CMOS logic. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that implements glue logic, bus interfacing, state machines, and address decoding through AND/OR arrays of macrocells. Within the broader hierarchy, CPLD -> programmable logic device (PLD) -> programmable logic IC -> logic semiconductor. Compared with FPGAs, CPLDs typically have lower logic density but deterministic timing, lower power, and instant-on behavior from on-chip EEPROM, which makes them ideal for control-plane rather than data-plane functions. Key features include 128 macrocells, 84 user I/O pins, a 15 ns propagation delay (tpd) at the commercial speed grade, and in-system programmability via the JTAG-compliant IEEE Std 1149.1 interface. The MAX 7000S architecture uses EEPROM process technology, allowing the configuration to be re-programmed in-circuit up to 100 times and retained for 20 years, eliminating external boot PROMs. The architecture combines a programmable interconnect array, macrocells with product-term-based logic synthesis, and programmable I/O cells that support 3.3 V or 5.0 V output levels. Each macrocell contains a programmable AND/OR array feeding a configurable flip-flop, and the I/O block can be set per-pin to input, output, or bidirectional mode. This makes the part a flexible bridge between processors, memories, and peripherals. Typical applications include bus address decoding and chip-select generation, glue logic between microprocessors and peripherals, state-machine control in industrial automation, peripheral interface bridging (PCI, ISA, VME), and post-PCB redesign fixes for digital logic that has already been laid out. The wide 5 V tolerance and 84 PLCC pins support legacy backplane designs where many control signals must be aggregated. When designing with this device, ensure that the JTAG chain order matches the BSDL file and that all unused I/O pins are left floating or tied to GND through a weak pulldown, per Altera application notes. The PLCC-84 socket must be a through-hole or socketed type if field upgrades are expected; for high-vibration environments a press-fit socket is recommended.
EPM7128SQC100-10 - MAX 7000S CPLD, 128 Macro, 84 I/O | Altera
The Altera (Intel) EPM7128SQC100-10 is a high-density, high-performance Complex Programmable Logic Device (CPLD) from the MAX 7000S family, featuring 128 macrocells, 2,500 usable gates, and 84 user I/O pins in a 100-pin PQFP (Plastic Quad Flat Pack) package. It is built on a 5V CMOS process with a 10 ns pin-to-pin logic delay, making it one of the most widely deployed 5V CPLDs in industrial glue-logic, bus-interface, and legacy replacement designs. What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instantly-on programmable logic device that sits between simple PAL/GAL devices and larger FPGAs. It uses an EEPROM- or flash-based architecture to retain configuration without a boot PROM, offers predictable timing with deterministic pin-to-pin delays, and is typically used for glue logic, address decoding, state-machine control, and bus-interface bridging. Within the programmable-logic hierarchy (PAL/GAL < CPLD < FPGA), the MAX 7000S family represents a mature, cost-effective tier for 5V systems. Key features include a 100 MHz maximum operating frequency, in-system programmability (ISP) via JTAG, programmable macrocell flipflops with individual clear, preset, clock, and clock-enable controls, open-drain output option, and pin compatibility with the wider MAX 7000S family. The device supports 5V core and I/O operation, with I/O pins tolerant of mixed-voltage interfacing. The EPM7128SQC100-10 uses a second-generation MAX architecture with a global interconnect fabric linking 16 Logic Array Blocks (LABs), each containing 8 macrocells. This architecture delivers fast, deterministic propagation delays that are critical for synchronous designs where setup/hold margins must be calculated precisely. The 100-pin PQFP package provides a low-cost, easy-to-inspect footprint for through-hole-style prototyping and rework. Typical applications include address decoding and bus interfacing for microprocessors and microcontrollers, glue logic between ASICs and standard peripherals, state-machine control in industrial controllers, legacy 5V system upgrades from discrete 74LS/74HC logic, and peripheral expansion for legacy parallel-port designs. Designers also use the EPM7128 family for I/O voltage translation and timing adjustment in mixed-voltage boards. When designing with this part, treat the 10 ns speed grade as the timing baseline: any design migrated from a faster grade (e.g., -6 or -7) must be re-checked for setup/hold at the new tPD. Decoupling requires 0.1 uF and 10 uF bulk caps near VCC pins, and unused JTAG TCK pins should be tied to GND through 1 kohm in noisy environments. This page synthesizes distributor pricing, drop-in alternatives (EPM7128SQC100-7, EPM7128SQC100-15N, EPM7128SQC100-10N), and practical design notes not found in the manufacturer datasheet alone, helping engineers shorten the selection and qualification cycle for legacy and 5V-tolerant designs.
EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
The Altera (Intel) EPM7128SQC100-10F is a high-density, high-performance CMOS Complex Programmable Logic Device (CPLD) from the MAX 7000S family, delivering 2,500 usable gates, 128 macrocells, and 84 user I/Os in a 100-pin Plastic Quad Flat Pack (PQFP) with a 10 ns pin-to-pin delay. The part is fabricated on advanced EEPROM-based process technology and operates from a single 5 V supply, providing in-system programmability (ISP) through a standard 4-pin JTAG interface (IEEE Std 1149.1). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style logic blocks (called macrocells or logic array blocks) on a single chip with a centralized programmable interconnect. Within the broader taxonomy, a CPLD sits below an FPGA in logic density but above a simple SPLD/PAL in functional integration, making it ideal for glue logic, bus interfacing, and control-plane state-machine tasks in mixed-signal systems. The MAX 7000S family specifically targets 5 V designs and offers deterministic, nanosecond-range timing that simplifies timing closure for asynchronous interfaces. Key features of the EPM7128SQC100-10F include counter frequencies up to 100 MHz, eight pin- or global-clock-driven logic array blocks, programmable power-saving mode that reduces each macrocell I/O current to a few microamperes, and individual macrocell register clear, preset, clock, and clock-enable controls. The 5 V tolerant I/O and 10 ns tPD make this part a long-standing choice for legacy industrial and telecommunications designs where noise margins and timing predictability matter more than raw gate count. Architecturally, the device uses a second-generation MAX architecture with a uniform interconnect that routes signals between LABs through a fast, predictable switch matrix. The non-volatile EEPROM cells retain configuration without external memory, allowing the device to behave as a standalone logic component on power-up with no boot time, which is critical for control-plane glue logic and bus-bridge designs. Typical applications include 5 V glue logic and bus interfacing (ISA, PCI, VME bridges), peripheral control for microcontrollers, address decoding and chip-select generation, state-machine and sequencer logic in industrial automation, telecommunications backplane glue, and legacy replacement for discrete 74-series TTL/CMOS logic on production boards. The 100-PQFP package also remains common in long-lifecycle industrial and aerospace designs. When designing with this part, confirm that 5 V tolerance is acceptable for downstream I/O banks; the 100-PQFP footprint is also offered in a -10N lead-free variant (EPM7128SQC100-10N) for RoHS-only builds. The 'F' suffix denotes a lead-free (Pb-free) finish, making the EPM7128SQC100-10F suitable for modern RoHS-compliant assembly while maintaining 5 V core operation. This page consolidates distributor pricing, in-system programming guidance, drop-in same-package alternatives (including the lead-free N-suffix and automotive I-suffix variants), and practical design notes not aggregated on the manufacturer datasheet cover page.