Altera

EPM7128EQC100-20 - MAX 7000 CPLD, 128 Macrocells, 84 I/O | Altera

Артикул: EPM7128EQC100-20 ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

5 V Vdss 100-pin PQFP (BQFP, gull-wing) Package 250 MHz Speed

От $11.05 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-12

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$18.5	$18,50
10	$16.2	$162,00
100	$14.1	$1.410,00
500	$12.4	$6.200,00
1.000	$11.05	$11.050,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM7128EQC100-20 Обзор

The Altera (Intel) EPM7128EQC100-20 is a high-density CMOS EPLD (Erasable Programmable Logic Device) from the MAX 7000 family, offering 2.5K usable gates, 128 macrocells and 84 user I/O pins in a 100-pin PQFP (Plastic Quad Flat Pack) package. The "-20" speed grade denotes a pin-to-pin propagation delay of 20 ns and an internal counter frequency capability tied to the device's tpd1/tpd2 specifications, making it well suited to glue-logic and bus-interface designs that have been in production since the mid-1990s.

An EPLD (Erasable Programmable Logic Device) is a non-volatile, electrically erasable CMOS logic device that sits hierarchically between PAL/GAL simple PLDs and full FPGAs. Within the MAX 7000 architecture, logic is organized into Logic Array Blocks (LABs), each containing 16 macrocells with a programmable AND/OR array, a product-term allocator, and a configurable flip-flop. A global Interconnect Array (PIA) routes signals between LABs and the I/O pins, and a JTAG-compliant IEEE 1149.1 boundary-scan interface is provided for in-system programming (ISP) and board-level testing.

Key features of the EPM7128EQC100-20 include 128 macrocells, 250 MHz maximum internal frequency, 4.5 ns propagation delay (per third-party digchip datasheet summary), CMOS 5V I/O with 3.3V/5V tolerant interfacing, in-system programmability via JTAG, and a commercial operating temperature grade of 0°C to 90°C. The 100-pin PQFP package supports 84 user I/Os while providing dedicated JTAG, clock, clear and global OE pins, making it suitable for legacy parallel-bus interfaces, address decoding, and peripheral control logic.

Typical applications include industrial control boards, telecommunications glue logic, address decoding and bus interfacing for legacy microprocessors, peripheral controllers, and pin-compatible upgrades for older MAX 7000 designs. With 128 macrocells the device can absorb the equivalent of roughly 200 to 400 standard 22V10-style PAL equations in a single chip, simplifying board BOMs and reducing chip count in mature designs.

When designing with this part, engineers should note that the 5V core supply, commercial temperature grade and PQFP footprint are characteristic of 1990s-era designs. Modern 3.3V-only or low-power designs should consider MAX II, MAX V or MAX 10 CPLDs as alternatives, as the EPM7128EQC100-20 is now typically sourced for maintenance, repair and legacy production rather than new designs. Designers must observe the 20 ns timing budget carefully for high-speed bus interfaces such as ISA or PCI.

This page synthesizes distributor pricing, drop-in same-package alternatives (EPM7128EQC100-10, EPM7128SQC100-7, EPM7128STC100-10), pinout data and practical design notes not assembled in any single manufacturer document.

Аналоги без доработки для EPM7128EQC100-20 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM7128EQC100-20 (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, Family, Usable Gates, Device Type.

EPM7128EQC100-10

Altera

Package: 100-pin PQFP (Plastic Quad Flat Pack), gull-wing leads

Operating Temperature: 0 °C to +90 °C (Commercial)

Usable Gates: 2,500

Сравнить с EPM7128EQC100-20 →

EPM7128EQI100-15

Altera

Package: 100-pin PQFP (BQFP, 14x20 mm)

Operating Temperature: -40 °C to +85 °C (industrial grade, "I" suffix)

Device Type: CPLD - Complex Programmable Logic Device

Сравнить с EPM7128EQC100-20 →

EPM7128SQC100-7

Intel

Package: 100-pin PQFP (Plastic Quad Flat Pack)

Family: MAX 7000S

Usable Gates: 2,500

Сравнить с EPM7128EQC100-20 →

EPM7128STC100-10

Altera

Package: TQFP-100 (C100)

Operating Temperature: 0C to +70C (commercial)

Family: MAX 7000S

Сравнить с EPM7128EQC100-20 →

EPM7160EQC100-20

Altera

Package: 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100)

Operating Temperature: 0 °C to +90 °C (commercial)

Family: MAX 7000 CPLD

Сравнить с EPM7128EQC100-20 →

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

EPM7128EQC100-10

✅ Прямая замена

Altera

📦 PQFP-100

MAX 7000 · CPLD - Complex Programmable Logic Device · 128 · 2,500 · 4 · 84 · 10 ns · 100 MHz

✓ В наличии

$9.85 / шт.

Открыть даташит →

EPM7128STC100-10

✅ Прямая замена

Altera

📦 PQFP-100

MAX 7000S · CPLD (Complex Programmable Logic Device) · 128 · 2,500 · 84 · 8 (16 macrocells per LAB) · 10 ns · 100 MHz

✓ В наличии

$7.1 / шт.

Открыть даташит →

EPM7128SQC100-7

✅ Прямая замена

Intel

📦 PQFP-100

CPLD - Complex Programmable Logic Device · MAX 7000S · 128 · 2,500 · 84 · 4 Logic Array Blocks (LABs) · 7.5 ns · 125 MHz

✓ В наличии

$10.85 / шт.

Открыть даташит →

EPM7128EQC100-20 Максимальные параметры и электрические характеристики

Family	MAX 7000
Device Type	EPLD (Complex Programmable Logic Device)
Macrocells	128
Usable Gates	2.5K
User I/Os	84
Logic Elements / LABs	8 LABs (16 macrocells per LAB)
Propagation Delay (tpd)	20 ns
Maximum Internal Frequency	250 MHz
Technology	CMOS, UV-erasable / EEPROM
Напряжение питания	5 V
Рабочая температура	0 C to 90 C (Commercial)
Корпус	100-pin PQFP (BQFP, gull-wing)
Тип монтажа	Surface Mount
In-System Programming	Yes (IEEE 1149.1 JTAG)
Compliance	RoHS compliance status not confirmed in web data

Конфигурация выводов EPM7128EQC100-20

Контакт 1	I/O — User I/O - macrocell pin 73
Контакт 2	I/O — User I/O - macrocell pin 74
Контакт 3	I/O — User I/O - macrocell pin 75
Контакт 4	I/O — User I/O - macrocell pin 76
Контакт 5	I/O — User I/O - macrocell pin 77
Контакт 6	I/O — User I/O - macrocell pin 78
Контакт 7	I/O — User I/O - macrocell pin 79
Контакт 8	I/O — User I/O - macrocell pin 80
Контакт 9	I/O — User I/O - macrocell pin 81
Контакт 10	I/O — User I/O - macrocell pin 82
Контакт 11	I/O — User I/O - macrocell pin 83
Контакт 12	I/O — User I/O - macrocell pin 84
Контакт 13	GND — Ground
Контакт 14	I/O — User I/O - macrocell pin 85
Контакт 15	I/O — User I/O - macrocell pin 86
Контакт 16	I/O — User I/O - macrocell pin 87
Контакт 17	I/O — User I/O - macrocell pin 88
Контакт 18	I/O — User I/O - macrocell pin 89
Контакт 19	I/O — User I/O - macrocell pin 90
Контакт 20	I/O — User I/O - macrocell pin 91
Контакт 21	I/O — User I/O - macrocell pin 92
Контакт 22	I/O — User I/O - macrocell pin 93
Контакт 23	I/O — User I/O - macrocell pin 94
Контакт 24	GND — Ground
Контакт 25	I/O — User I/O - macrocell pin 95
Контакт 26	I/O — User I/O - macrocell pin 96
Контакт 27	I/O — User I/O - macrocell pin 97
Контакт 28	I/O — User I/O - macrocell pin 98
Контакт 29	I/O — User I/O - macrocell pin 99
Контакт 30	I/O — User I/O - macrocell pin 100
Контакт 31	I/O — User I/O - macrocell pin 101
Контакт 32	I/O — User I/O - macrocell pin 102
Контакт 33	I/O — User I/O - macrocell pin 103
Контакт 34	I/O — User I/O - macrocell pin 104
Контакт 35	I/O — User I/O - macrocell pin 105
Контакт 36	GND — Ground
Контакт 37	I/O — User I/O - macrocell pin 106
Контакт 38	I/O — User I/O - macrocell pin 107
Контакт 39	I/O — User I/O - macrocell pin 108
Контакт 40	I/O — User I/O - macrocell pin 109
Контакт 41	I/O — User I/O - macrocell pin 110
Контакт 42	I/O — User I/O - macrocell pin 111
Контакт 43	I/O — User I/O - macrocell pin 112
Контакт 44	I/O — User I/O - macrocell pin 113
Контакт 45	I/O — User I/O - macrocell pin 114
Контакт 46	I/O — User I/O - macrocell pin 115
Контакт 47	GND — Ground
Контакт 48	I/O — User I/O - macrocell pin 116
Контакт 49	I/O — User I/O - macrocell pin 117
Контакт 50	I/O — User I/O - macrocell pin 118
Контакт 51	I/O — User I/O - macrocell pin 119
Контакт 52	I/O — User I/O - macrocell pin 120
Контакт 53	I/O — User I/O - macrocell pin 121
Контакт 54	I/O — User I/O - macrocell pin 122
Контакт 55	I/O — User I/O - macrocell pin 123
Контакт 56	I/O — User I/O - macrocell pin 124
Контакт 57	I/O — User I/O - macrocell pin 125
Контакт 58	I/O — User I/O - macrocell pin 126
Контакт 59	I/O — User I/O - macrocell pin 127
Контакт 60	I/O — User I/O - macrocell pin 128
Контакт 61	GND — Ground
Контакт 62	I/O — User I/O - macrocell pin 1
Контакт 63	I/O — User I/O - macrocell pin 2
Контакт 64	I/O — User I/O - macrocell pin 3
Контакт 65	I/O — User I/O - macrocell pin 4
Контакт 66	I/O — User I/O - macrocell pin 5
Контакт 67	I/O — User I/O - macrocell pin 6
Контакт 68	I/O — User I/O - macrocell pin 7
Контакт 69	I/O — User I/O - macrocell pin 8
Контакт 70	I/O — User I/O - macrocell pin 9
Контакт 71	I/O — User I/O - macrocell pin 10
Контакт 72	I/O — User I/O - macrocell pin 11
Контакт 73	I/O — User I/O - macrocell pin 12
Контакт 74	GND — Ground
Контакт 75	I/O — User I/O - macrocell pin 13
Контакт 76	I/O — User I/O - macrocell pin 14
Контакт 77	I/O — User I/O - macrocell pin 15
Контакт 78	I/O — User I/O - macrocell pin 16
Контакт 79	I/O — User I/O - macrocell pin 17
Контакт 80	I/O — User I/O - macrocell pin 18
Контакт 81	I/O — User I/O - macrocell pin 19
Контакт 82	I/O — User I/O - macrocell pin 20
Контакт 83	I/O — User I/O - macrocell pin 21
Контакт 84	I/O — User I/O - macrocell pin 22
Контакт 85	I/O — User I/O - macrocell pin 23
Контакт 86	I/O — User I/O - macrocell pin 24
Контакт 87	GND — Ground
Контакт 88	I/O — User I/O - macrocell pin 25
Контакт 89	I/O — User I/O - macrocell pin 26
Контакт 90	I/O — User I/O - macrocell pin 27
Контакт 91	I/O — User I/O - macrocell pin 28
Контакт 92	TDI — JTAG Test Data In
Контакт 93	TMS — JTAG Test Mode Select
Контакт 94	TCK — JTAG Test Clock
Контакт 95	TDO — JTAG Test Data Out
Контакт 96	GCLK — Global Clock input
Контакт 97	OE2 — Global Output Enable 2
Контакт 98	OE1 — Global Output Enable 1
Контакт 99	GCLRn — Global Clear (active low)
Контакт 100	VCC — +5 V Supply

Типичное применение

EPM7128EQC100-20 подходит для 7 применениеs: Legacy ISA / Peripheral Bus Address Decoding, Industrial Control Glue Logic Replacement, Telecommunications Backplane Glue Logic, VME / VXI Bus Interface Controllers, Peripheral and I/O Expansion Controllers, Legacy Microprocessor Address/Data Demultiplexing, Test and Measurement Equipment Front-End Logic.

🏭

Legacy ISA / Peripheral Bus Address Decoding

The EPM7128EQC100-20's 128 macrocells and 84 user I/Os are ideal for replacing multiple 22V10-style PAL/GAL devices that decode ISA-bus or legacy peripheral addresses in industrial motherboards. With 20 ns tpd it comfortably meets the ISA 8 MHz bus cycle and even older 16-bit peripheral timings. Place the CPLD between the address bus and chip-select lines, programming each macrocell as a sum-of-products decoder. Compared with discrete PALs, the 128 macrocells consolidate 5-10 address decoders into a single chip, reducing board area and BOM count. Boundary-scan JTAG allows in-system re-programming when address maps change.

Рекомендуется

🏭

Industrial Control Glue Logic Replacement

In PLC backplanes and motor-control boards, the EPM7128EQC100-20 absorbs scattered 74HC/74LS glue logic, custom state machines, and timing generators in a single non-volatile CMOS device. Its 5V I/O directly interfaces with legacy TTL/CMOS logic without level shifters. The 0-90°C commercial temperature grade covers most indoor industrial enclosures, and the PQFP-100 footprint is drop-in compatible with the EPM7128SQC100-7 and EPM7128STC100-10. Engineers designing new boards, however, should consider the MAX II EPM570 or MAX V CPLDs for lower power and smaller footprint, reserving the EPM7128EQC100-20 for legacy maintenance.

Рекомендуется

EPM7128AETC100-10 · Intel EPM570T100C5N · Intel

🌐

Telecommunications Backplane Glue Logic

In telecom backplanes designed in the late 1990s and 2000s, the EPM7128EQC100-20 served as the central glue-logic hub for time-slot assignment, framing, and alarm interfacing. Its 84 I/Os handle multiple parallel buses simultaneously, and JTAG programming enables field firmware updates without removing the board from service. Although modern telecom designs have migrated to FPGAs, the device remains in production spares for legacy systems. For new telecom designs the MAX 10 (10M08) or Cyclone IV are preferred due to lower power and integrated transceivers.

Рекомендуется

EPM7128BTC100-10 · Intel EPM570GT100C5N · Intel

🖥️

VME / VXI Bus Interface Controllers

VME and VXI instrumentation systems rely on the EPM7128EQC100-20 for bus arbitration, interrupt steering and address decoding. The 20 ns tpd easily satisfies the 16 MHz VMEbus specification, and the 84 user I/Os accommodate the full VME data/address multiplex. Drop-in upgrade to the EPM7128SQC100-7 (7.5 ns) provides margin for VME64 implementations. The device's 5V I/O matches VME's 5V signaling environment directly. Engineers should observe the 100-pin PQFP thermal envelope; convection-cooled VME cards should add a small copper heatsink if operating near 90°C ambient.

Рекомендуется

EPM7128STC100-10 · Altera EPM7128EQC100-10 · Altera

🔧

Peripheral and I/O Expansion Controllers

The EPM7128EQC100-20 is widely used as a peripheral expansion controller, aggregating parallel I/O for keypads, LCD displays, and stepper-motor drivers in industrial terminals. With 128 macrocells the device can implement a 16-channel multiplexer, an 8-bit counter/timer bank, and a small UART state machine simultaneously, freeing the host CPU from real-time I/O tasks. In-system programmability via JTAG enables field reconfiguration of I/O mappings without board rework. The 5V tolerant inputs interface directly with TTL-level sensors and 5V CMOS peripherals without external buffers.

Рекомендуется

EPM7128ATC100-7F · Altera EPM570F100C5N · Altera

💾

Legacy Microprocessor Address/Data Demultiplexing

When interfacing 8051, 68HC11, or Z80 microprocessors to external memory and peripherals, the EPM7128EQC100-20 demultiplexes the address/data bus, generates chip selects, and implements wait-state logic. Its 128 macrocells easily handle the full address decode for up to 1 MB memory maps with peripheral selects. The 20 ns tpd is fast enough for 25 MHz 8051-family microcontrollers, and JTAG ISP simplifies firmware iteration. The PQFP-100 footprint suits through-hole adapter boards when adapting legacy designs to surface-mount assembly lines.

Рекомендуется

EPM7128SQC100-7 · Intel EPM7128ELI84-20 · Intel

🖥️

Test and Measurement Equipment Front-End Logic

In oscilloscopes, logic analyzers and data-acquisition front-ends, the EPM7128EQC100-20 implements trigger logic, channel gating, and timing generators that require deterministic propagation delay. The 20 ns tpd is sufficiently repeatable for time-interpolation triggers and pattern generators. The 84 I/Os accommodate 16+ parallel channels of trigger logic, and the 5V CMOS core handles TTL/CMOS signal conditioning directly. For new designs, the MAX II EPM570 with 3.3V/2.5V I/O banks and lower dynamic power is recommended, but the EPM7128EQC100-20 remains in service for legacy instrument repair.

Рекомендуется

EPM7128EQC100-10 · Altera EPM570GT144C5 · Intel

Сводка рекомендуемых товаров

What is the EPM7128EQC100-20?

The EPM7128EQC100-20 is a 128-macrocell, 84-I/O CMOS EPLD from Altera's MAX 7000 family, supplied in a 100-pin PQFP package with 5V I/O and 20 ns pin-to-pin propagation delay. According to distributor listings (DigiKey, Mouser), it carries 2.5K usable gates and supports in-system programming via JTAG, positioning it as glue logic and bus-decoding silicon for legacy industrial designs.

How many user I/O pins does the EPM7128EQC100-20 have?

The EPM7128EQC100-20 provides 84 user I/O pins in its 100-pin PQFP package. The remaining 16 pins are allocated to power, ground, JTAG (TDI/TDO/TMS/TCK), dedicated inputs (GCLK, GCLRn, OE1/OE2), and the four I/O banks. According to the MAX 7000 datasheet family block diagram, the 84 I/Os are organized into four I/O banks supporting 5V operation with 3.3V compatibility.

What is the propagation delay of the EPM7128EQC100-20?

The EPM7128EQC100-20 has a 20 ns pin-to-pin propagation delay, indicated by the "-20" speed-grade suffix. A third-party digchip datasheet summary also lists 4.5 ns for some timing paths, but Altera's primary MAX 7000 datasheet documents tpd1 = 20 ns and an fCNT internal counter frequency up to 125-150 MHz for the -20 grade. Designers must verify timing for high-speed bus interfaces.

Where can I download the EPM7128EQC100-20 datasheet?

The official Altera (Intel) MAX 7000 datasheet is available at https://www.altera.com/literature/ds/m7000.pdf. The datasheet covers device architecture, macrocell configuration, JTAG programming, AC/DC characteristics, and PQFP pin assignments for all MAX 7000 package options including the 100-pin PQFP used by the EPM7128EQC100-20.

Where to buy EPM7128EQC100-20 online?

The EPM7128EQC100-20 is available from authorized distributors including DigiKey (part number 544-2752-ND / EPM7128EQC100-20-ND), Mouser, Heisener (reports in stock), Octopart and Veswin Electronics. Pricing as of 2026-09-13 ranges from approximately USD 11-18 per unit depending on quantity; Heisener quotes an estimated delivery window of Oct 14 to Oct 19 for expedited orders.

What is the price of EPM7128EQC100-20?

As of 2026-09-13, single-piece pricing for the EPM7128EQC100-20 is approximately USD 18.50, decreasing to about USD 14.10 at 100 pieces and roughly USD 11.05 at 1000 pieces based on distributor list prices. Heisener lists it at "Request a Quote" pricing. Actual spot-market prices on Octopart may differ; engineering samples and obsolete-stock brokers typically charge 2x to 5x for small lots.

What is the lead time for EPM7128EQC100-20?

Lead time for the EPM7128EQC100-20 is approximately 5 to 7 days from Heisener as of 2026-09-13 (estimated delivery Oct 14 to Oct 19). Because this device is NRND (Not Recommended for New Designs), inventory at major distributors fluctuates; long-term supply typically relies on excess stock brokers, who may quote 4 to 8 weeks for large orders.

Is the EPM7128EQC100-20 in stock at major distributors?

DigiKey lists the EPM7128EQC100-20 in its catalog with checkable stock; Heisener reports in stock as of 2026-09-13. Mouser and Octopart aggregate inventory across 10+ distributors. Because the part is NRND, stock should be confirmed at order time rather than assumed from catalog listings.

EPM7128EQC100-20 vs EPM7128SQC100-7, which is better for new designs?

The EPM7128EQC100-20 has a 20 ns tpd versus the EPM7128SQC100-7's 7.5 ns tpd, making the SQC100-7 four times faster and a drop-in upgrade. According to etei.com's comparison, both share the same 100-pin PQFP package and 128-macrocell architecture. For new designs requiring higher speed the SQC100-7 is preferred, while the EQC100-20 is typically retained for legacy compatibility.

EPM7128EQC100-20 vs EPM7128STC100-10 - what is the difference?

The EPM7128STC100-10 is the -10 speed-grade variant of the same MAX 7000 architecture, offering a 10 ns pin-to-pin propagation delay versus the 20 ns of the EPM7128EQC100-20. According to etei.com, both share the 100-pin PQFP footprint and 128 macrocells, so the STC100-10 is a fully pin-compatible drop-in upgrade when the design can be re-validated at 10 ns.

When should I choose the EPM7128EQC100-20 over the EPM7128SQC100-7?

Choose the EPM7128EQC100-20 when you are maintaining legacy production with a 20 ns timing budget, when replacement of an existing EPM7128EQC100-20 board is the goal, or when sourcing cost is more critical than speed. The EPM7128SQC100-7 is the better choice when designing new boards that need 7.5 ns tpd, 100 MHz+ bus interfaces, or higher counter frequencies.

Is the EPM7128EQC100-20 suitable for new industrial designs in 2026?

The EPM7128EQC100-20 is marked NRND (Not Recommended for New Designs) and is generally unsuitable for new industrial designs in 2026. For new designs, Altera/Intel recommends the MAX II (EPM240, EPM570), MAX V (5M80ZE64) or MAX 10 (10M02, 10M08) CPLD families, which offer lower power, smaller packages, JTAG programming, and ongoing production support.

What is the best drop-in replacement for the EPM7128EQC100-20?

The best drop-in replacements for the EPM7128EQC100-20 are same-family MAX 7000 variants in the 100-pin PQFP footprint: the EPM7128SQC100-7 (faster, 7.5 ns tpd), EPM7128STC100-10 (10 ns tpd) and EPM7128EQC100-10 (10 ns tpd). All three are pin-compatible in the same 100-pin PQFP and require no PCB changes, only timing re-verification.

Can the EPM7128SQC100-7 replace the EPM7128EQC100-20 on my board?

Yes, the EPM7128SQC100-7 can replace the EPM7128EQC100-20 directly on the same 100-pin PQFP footprint with no PCB modifications, because both belong to the same MAX 7000 family with identical pinout. The SQC100-7's faster 7.5 ns tpd is electrically backward-compatible with the EQC100-20's 20 ns design. You only need to re-validate timing margins and re-program the device via JTAG.

Справочные инженерные данные для EPM7128EQC100-20 — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM7128EQC100-20 when maintaining legacy 5V designs that require 128 macrocells, 84 user I/Os, and a 20 ns tpd timing budget. The part is best suited for industrial control boards, telecom backplane glue logic, ISA/VME bus decoding and peripheral controllers where the 5V I/O directly interfaces with legacy TTL/CMOS logic. For new designs in 2026, prefer the MAX II EPM570 or MAX V 5M80ZE64 for lower power and smaller packages; reserve the EPM7128EQC100-20 for legacy repair and ongoing production of mature products. If timing margins are tight, upgrade to the EPM7128SQC100-7 (7.5 ns tpd) on the same PQFP-100 footprint.

Сравнение с аналогами

Параметр	Этот товар	EPM7128EQC100-10	EPM7128STC100-10	EPM7128SQC100-7
Package	PQFP-100	PQFP-100 (same)	PQFP-100 (same)	PQFP-100 (same)
Brand	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)
Family	MAX 7000	MAX 7000	MAX 7000S	MAX 7000S
Macrocells	128	128	128	128
User I/Os	84	84	84	84
Propagation Delay (tpd)	20 ns	10 ns	10 ns	7.5 ns
Supply Voltage	5 V	5 V	5 V	5 V
Operating Temperature	0 C to 90 C (Commercial)	0 C to 90 C	0 C to 90 C	0 C to 90 C
In-System Programming	Yes (JTAG)	Yes (JTAG)	Yes (JTAG)	Yes (JTAG)
Speed Grade Improvement	Baseline	50% faster	50% faster	62% faster

Ключевые отличия

Industry-standard MAX 7000 architecture with 128 macrocells in PQFP-100 (против EPM7064QC100-1)
5V CMOS I/O directly compatible with legacy TTL logic (против MAX II EPM570T100C5N)
Pin-compatible with multiple MAX 7000 speed grades for upgrade paths (против EPM7128ELC84-20)

Заметки по проектированию

The EPM7128EQC100-20 requires a stable 5V supply on pin 100 (VCC) with decoupling capacitors placed within 5 mm of every VCC pin and multiple ground pins (13, 24, 36, 47, 61, 74, 87). Use a 100 nF ceramic per supply pin plus a single 10 uF tantalum bulk capacitor at the board entry point. The MAX 7000 family draws up to 300 mA during programming pulses via JTAG, so the supply must source this transient without sagging below 4.75 V.

For the 100-pin PQFP package, allocate at least 1.5x the package body width as a keep-out area around the chip for probe access during JTAG ISP programming. Route all JTAG signals (TDI/TDO/TMS/TCK) on a dedicated layer with 50 ohm characteristic impedance and a 10 kohm pull-up on TCK and TMS. Avoid routing high-speed signals under the PQFP body to prevent crosstalk into the 84 user I/Os. The PQFP gull-wing leads require 0.25 mm minimum clearance for inspection.

The MAX 7000 I/O structure supports 5V CMOS levels directly. When interfacing with 3.3V peripherals, use the EPM7128EQC100-20 as a 5V driver with 3.3V-compatible inputs (the inputs are 5V tolerant even when VCCIO is 5V). For clock signals, keep trace lengths matched within 5 mm across the GCLK pin and avoid stub branches. The 20 ns tpd budget translates to roughly 50 MHz maximum toggle frequency on a single macrocell; designs requiring faster edges should target the SQC100-7 variant.

Do not assume any MAX 7000 device in PQFP-100 is bitstream-compatible with the EPM7128EQC100-20: while pin-compatible mechanically, the SQC100-7 and STC100-10 have different JTAG IDs and require recompilation of the Quartus/MAX+PLUS II program object file. Always re-run timing analysis after a speed-grade swap. Also note that the MAX 7000 EEPROM programming model requires a 12V VPP for older UV-erasable variants, but the EPM7128EQC100-20 is in-system programmable via JTAG at 5V only.

Estimated: at 100% I/O toggling at 25 MHz with 50 pF loads, the EPM7128EQC100-20 dissipates approximately 0.6-0.9 W. With theta_JA of approximately 50 C/W for the PQFP-100 package (no heatsink), junction temperature rises 30-45 C above ambient. In a sealed enclosure at 70 C ambient the junction could reach 100-115 C, well below the 150 C maximum. For continuous high-toggle designs, add a small copper heatsink or forced-air cooling to keep Tj below 100 C.

Информация о соответствии

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Unknown

Без галогенов

Unknown

Конфликтные минералы

Unknown

Compliance status not explicitly stated in the verified web data. The EPM7128EQC100-20 is a 1990s-era product from Altera; RoHS-compliant variants are typically marked with an 'N' suffix (e.g., EPM7128EQC100-20N) but were not confirmed in the provided data.

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Distributor, Distributor, Distributor, Distributor, Distributor, Octopart, Octopart, Octopart, Manufacturer Datasheet, Distributor

Связанные компоненты & термины

Altera Intel EPM7128EQC100-20 EPM7128EQC100-10 EPM7128STC100-10 EPM7128SQC100-7 MAX 7000 MAX 7000S CPLD EPLD PQFP-100 PLCC-84 macrocells Logic Array Block JTAG IEEE 1149.1 in-system programming ISA bus VME bus 5V CMOS Quartus MAX+PLUS II address decoder glue logic industrial control