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EP4SGX70HF35C3G - Stratix IV GX 72.6K LE FPGA, 1152-FBGA | Intel
EP4SGX70HF35C3G

EP4SGX70HF35C3G - Stratix IV GX 72.6K LE FPGA, 1152-FBGA | Intel

The Intel EP4SGX70HF35C3G is a high-density Stratix IV GX Field Programmable Gate Array (FPGA) from Intel's Stratix IV GX family, delivering 72,600 logic elements, 2,904 LABs/CLBs, and 7,564,880 bits of embedded RAM in a 1152-ball FineLine BGA package (35 mm × 35 mm). It integrates up to 488 user I/O pins and 8 integrated transceivers capable of 3.125 Gbps, targeting high-bandwidth serial connectivity for wired communications, broadcast, and high-performance digital designs. The device is built on a 40 nm low-power process and operates from a 0.87 V to 0.93 V core supply with 0°C to 85°C commercial-grade junction temperature. An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) belonging to the broader category of integrated circuits (ICs) > semiconductor devices. Within the digital logic hierarchy, FPGAs sit between ASICs (Application-Specific Integrated Circuits) and CPLDs (Complex Programmable Logic Devices), offering the highest logic density, the most flexible I/O architecture, and on-chip memory blocks, DSP blocks, and high-speed serial transceivers. FPGA hierarchy: FPGA > PLD > logic IC > integrated circuit > semiconductor. FPGAs are widely used as prototyping platforms, custom compute accelerators, and production-volume silicon in networking, defense, industrial imaging, and test equipment. Key features of the EP4SGX70HF35C3G include dedicated on-chip memory of 7.5 Mbit, 488 user I/Os, embedded 8B/10B-compatible transceivers supporting PCI Express Gen1, Gigabit Ethernet, Serial RapidIO, and basic SerialLite II protocols. The HF35 speed grade targets higher Fmax performance for time-critical paths. The C3 suffix denotes a commercial temperature grade (0°C to 85°C). Built-in configuration options include Passive Serial, Fast Passive Parallel, Active Serial, and JTAG, supported by the Quartus II design toolchain. Typical applications include high-speed serial interface bridging (PCIe Gen1, GbE, CPRI/OBSAI backhaul), broadcast video processing, military and avionics signal processing, ASIC prototyping, and high-throughput data-acquisition systems. When designing with the EP4SGX70HF35C3G, engineers should plan PCB layer stack-up for the 35 mm FC-FBGA with at least 12 layers for proper transceiver signal integrity. Thermal management via heatsink or chassis airflow is required for sustained high-utilization workloads. This page synthesizes distributor pricing, drop-in alternatives from the Stratix IV GX family, and practical design notes not found in the manufacturer datasheet alone.

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EP4SGX70HF35C4G - Stratix IV GX FPGA 70K LEs, 1152-FBGA | Intel
EP4SGX70HF35C4G

EP4SGX70HF35C4G - Stratix IV GX FPGA 70K LEs, 1152-FBGA | Intel

The Intel (formerly Altera) EP4SGX70HF35C4G is a high-density Stratix IV GX Field-Programmable Gate Array built on a 40 nm low-power process, integrating approximately 72,600 logic elements, 7,564,880 bits of embedded memory, and 488 user I/Os in a 1152-ball FineLine BGA (FCBGA) package. Operating from a 0.9 V core supply, the device belongs to the Stratix IV GX family and is speed grade C4 (commercial, 0 to 85 C). What is a Stratix IV GX FPGA? It is a high-performance programmable logic device from the Stratix family that combines general-purpose logic fabric, dedicated DSP blocks, embedded memory, and integrated multi-gigabit transceivers (MGTs) for high-speed serial I/O. Within the Intel/Altera taxonomy it sits under: FPGA -> programmable logic -> semiconductor device. Stratix IV GX parts target high-bandwidth wireline, wireless, broadcast, and high-performance digital signal processing designs that need both serial connectivity and large parallel fabric. Key specifications include up to 8 integrated transceivers running up to 8.5 Gbps per channel, hard PCIe Gen1/Gen2 IP cores, embedded memory up to 7.5 Mb (RAM), and dedicated variable-precision DSP blocks supporting 18x18 and 36x36 multipliers. The 1152-ball FCBGA package supports high I/O count with flip-chip attach for improved signal integrity and thermal performance. Typical applications include 10G/40G Ethernet bridging, PCIe Gen2 endpoint/root complex designs, high-speed serial backplane aggregation, ASIC prototyping, and high-performance DSP pipelines such as radar, medical imaging, and software-defined radio front-ends where the device balances serial bandwidth with parallel fabric throughput. When designing with this part, pay close attention to power-rail sequencing (core 0.9 V, transceiver PLL, I/O banks), PCB escape routing for the 1152-ball BGA, and thermal management. This page consolidates current distributor pricing, drop-in alternatives in the same 1152-FBGA footprint, and practical design notes that are not found in the manufacturer datasheet alone.

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EP4SGX70HF35I3G - 72.6K LE Stratix IV GX FPGA, FCBGA-1152 | Intel
EP4SGX70HF35I3G

EP4SGX70HF35I3G - 72.6K LE Stratix IV GX FPGA, FCBGA-1152 | Intel

The Intel EP4SGX70HF35I3G is a high-density Stratix IV GX field-programmable gate array (FPGA) with 72,600 logic elements, 7,564,880 bits of embedded memory, and 29,040 adaptive logic modules (ALMs), housed in a 1152-ball flip-chip BGA (FCBGA) package. It integrates up to 480 user I/Os, multi-gigabit transceivers, and 488 (18x18) multipliers, all manufactured on TSMC's 40 nm process node with a core supply of 950 mV. An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit whose logic functionality is defined by customer configuration after manufacturing, rather than at the fab. FPGAs sit in the hierarchy of programmable logic devices (PLD) -> CPLD -> FPGA -> structured ASIC, and serve as the highest-density programmable platform for digital signal processing, high-speed serial I/O, and parallel datapath designs. The Stratix IV family specifically targets high-performance, transceiver-rich applications such as wireline telecom, military radar, and high-end test and measurement. Key features of the EP4SGX70HF35I3G include 9 integrated transceivers capable of up to 8.5 Gbps data rates (GX variant), 7.20 Mbit of embedded SRAM organized as M9K and M144K blocks, support for DDR/DDR2/DDR3/QDR II/QDR II+ external memory interfaces, and 4 phase-locked loops (PLLs) per device quadrant. The I3 speed grade and -40C to +100C industrial temperature range make it suitable for harsh-environment deployments while still meeting demanding timing budgets. Architecture-wise, the device uses Altera's Logic Array Blocks (LABs) containing 8 ALMs each, with routing driven by MultiTrack interconnect and DirectDrive technology. Transceiver tiles are arranged adjacent to the I/O banks on the device periphery, with PCS and PMA blocks supporting protocols such as PCIe Gen1/Gen2, XAUI, CPRI, and Serial RapidIO. The 1152-ball FCBGA utilizes a 35 mm x 35 mm substrate with 1.0 mm ball pitch, requiring high-density PCB manufacturing. Typical applications include 10G Ethernet line cards, baseband processing for wireless infrastructure, video broadcast and imaging pipelines, military secure-communication modems, and high-channel-count data acquisition systems. Its combination of transceivers, DSP blocks, and large memory makes it especially effective for signal-processing pipelines requiring both packet handling and parallel arithmetic. When designing with this FPGA, prioritize signal-integrity-aware stackup design for the FCBGA footprint, allocate sufficient decoupling (typically 0.1 uF, 1 uF, and bulk capacitance) around each transceiver tile power pin, and validate pin assignments against the Quartus II pin-out file before layout commit. Industrial-grade I3 silicon requires proper thermal management to keep junction temperature below 100C at full transceiver utilization. This page synthesizes distributor pricing, same-family pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet alone.

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EP4SGX70HF35I4G - Stratix IV GX FPGA 72.6K LE 488 I/O | Intel
EP4SGX70HF35I4G

EP4SGX70HF35I4G - Stratix IV GX FPGA 72.6K LE 488 I/O | Intel

The Intel (formerly Altera) EP4SGX70HF35I4G is a Stratix IV GX family Field Programmable Gate Array (FPGA) fabricated on a 40 nm low-power process, integrating 72,600 logic elements, 7,564,880 bits of embedded memory, and 488 user I/Os in a 1152-ball FCBGA package. The -I4G speed/temperature grade designation indicates an industrial temperature range and a specific speed bin targeting transceiver-rich applications. The HF35 package variant is a high-density flip-chip BGA with 35 mm pitch optimized for high-speed serial I/O performance. The part carries the -I4G suffix meaning industrial (-40C to +100C ambient) operating range with a specific transceiver speed bin commonly used in communications infrastructure. A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, dedicated DSP blocks, high-speed transceivers, and on-chip memory that an engineer can reconfigure after manufacturing to implement custom digital logic. FPGAs sit between standard ASICs (custom silicon, high NRE, long lead time) and microcontrollers (fixed architecture, software-defined) in the system hierarchy: programmable logic device -> logic IC -> integrated circuit -> semiconductor. Modern high-end FPGAs like the Stratix IV GX family are used as system-on-chip integration platforms where hardware acceleration, parallel DSP, and multi-gigabit serial I/O must coexist on a single die. Key features of the EP4SGX70HF35I4G include 8 integrated transceivers supporting data rates commonly used in PCI Express Gen1/Gen2 and Gigabit Ethernet, hard memory controllers for DDR3/DDR2 interfaces, dedicated 18x18 multiplier blocks for DSP, up to 488 user I/O pins supporting multiple I/O standards including LVDS, LVTTL, and LVCMOS, and configuration via JTAG or serial configuration devices. The device also provides up to 24 full-duplex CDR-capable transceivers and 4 hard PCIe Gen1/Gen2 IP blocks depending on the Stratix IV GX variant. The high-pin-count 1152-ball FCBGA package exposes both transceiver channels and high-bandwidth parallel I/O for communications and DSP line cards. The Stratix IV architecture combines a hardened transceiver physical layer with partial reconfiguration, adaptive logic modules (ALMs), and TriMatrix embedded memory, enabling designers to pipeline parallel DSP workloads while keeping the device footprint small. Hard PCIe, SERDES, and memory controllers reduce soft IP overhead, allowing higher effective logic utilization for application code. Typical applications include 10G/40G optical transport line cards, software-defined radio baseband processing, ASIC prototyping, high-performance DSP coprocessors, and PCIe accelerator cards. The combination of industrial temperature range and high transceiver count makes this part well-suited to carrier-grade networking equipment and military/aerospace signal processing. When designing with this part, allocate PCB layer budget for the 1152-ball FCBGA escape routing, provide low-jitter reference clocks for the transceivers, and follow Altera/Intel power regulator guidelines for the Stratix IV device family (typically requiring multiple buck converters for core, I/O, and PLL supplies). This page synthesizes distributor stock, lifecycle status, and drop-in Stratix IV family alternatives that share the same HF35 1152-ball FCBGA footprint, giving engineers a faster procurement decision than the manufacturer product page alone.

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EP610DC-10 - 16-Macrocell Classic EPLD, 10ns, 24-Pin CDIP | Intel
EP610DC-10

EP610DC-10 - 16-Macrocell Classic EPLD, 10ns, 24-Pin CDIP | Intel

The Intel (formerly Altera) EP610DC-10 is a 16-macrocell Classic EPLD from the original Altera Classic device family, fabricated on advanced CMOS technology and packaged in a 24-pin ceramic DIP (CDIP). It delivers pipelined data rates up to 100 MHz with a 10 ns pin-to-pin propagation delay (-10 speed grade), making it one of the earliest high-density programmable logic devices for glue-logic and state-machine integration. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits between simple PAL/GAL devices and modern CPLDs/FPGAs in the PLD hierarchy: PLD -> EPLD -> CPLD -> FPGA -> programmable logic -> semiconductor. EPLDs use non-volatile EEPROM or EPROM storage to retain configuration at power-off, and provide predictable combinational and registered logic with deterministic timing - ideal for replacing multiple SSI/MSI discrete logic gates in a single package. Key features of the EP610DC-10 include 16 macrocells, 24 I/O pins in the CDIP-24 windowed-ceramic package, 100 MHz pipelined throughput, and a propagation delay of 10 ns at the commercial temperature range. The Classic architecture provides a programmable AND/OR array feeding 16 output macrocells, each containing a programmable flip-flop for synchronous logic. EPROM-based configuration allows unlimited reprogramming when the device is erased under UV light through the quartz window on the top of the ceramic package. The EP610DC-10's 24-pin ceramic DIP is windowed (erasable) and uses through-hole mounting, suitable for prototype, lab, and legacy industrial systems. The 'DC' suffix indicates the CDIP-24 ceramic DIP package, while '-10' denotes the 10 ns speed grade. The device requires a single 5V supply and supports TTL-compatible I/O. Applications include legacy industrial control, address decoding, state machines, and bus-interface glue logic in older computer and telecom designs. Designers should note the ceramic DIP package requires through-hole PCB mounting and a UV eraser for reprogramming. This EP610DC-10 is an obsolete/EOL part; sourcing is limited to the secondary market, and modern alternatives should be evaluated for new designs.

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EP610DC-15 - 16 Macrocell Classic EPLD, 17ns tPD | Altera
EP610DC-15

EP610DC-15 - 16 Macrocell Classic EPLD, 17ns tPD | Altera

The Altera EP610DC-15 is a member of the Classic EPLD family, providing 16 macrocells in a UV-erasable, CMOS PAL-type architecture housed in a 24-pin ceramic DIP (CDIP) package. The -15 speed grade delivers a 15 ns pin-to-pin propagation delay (typical tPD of 17 ns over commercial conditions) and supports a maximum internal clock frequency of 71.4 MHz, making it a drop-in replacement for TTL-era 24-pin PAL/GAL devices in glue-logic applications. A Classic EPLD (Erasable Programmable Logic Device) is the predecessor to modern CPLDs (Complex Programmable Logic Devices). It is a non-volatile, reprogrammable logic IC that combines the simplicity of PAL architecture with the density of multiple PAL-like macrocell arrays on a single die. The Classic EPLD sits within the broader taxonomy: programmable logic -> PLD -> EPLD -> CMOS EPLD -> Classic EPLD family. Compared to modern CPLDs, Classic EPLDs offer lower density but retain useful advantages: deterministic timing, simple JEDEC fuse-map programming, and 5V tolerant I/O. The device features 20 dedicated inputs and 16 bidirectional I/O pins, organized as four Logic Expanders with 160 total product terms, supporting sum-of-products Boolean implementation through a fixed AND/OR/three-state structure. The EP610DC-15 operates from a single 5 V supply (4.75 V to 5.25 V) and offers a typical quiescent current around 50 mA, with commercial 0C to 70C operating range as denoted by the DC package code. Architecture-wise, the EP610 uses Altera's Classic AND-OR architecture with each macrocell providing a programmable D/T/J-K flip-flop, four product terms for logic, and one output enable product term. Programming is performed using a standard JEDEC fuse map via Altera's programming hardware; the UV window in the ceramic DIP enables erasure by exposure to ultraviolet light, hence the name UV PLD. Typical applications include bus decoding and address mapping in 8086/68K microprocessor systems, state-machine replacement for SSI/MSI logic, I/O decoding and wait-state generation, and TTL-to-CMOS logic consolidation. It is also used in legacy industrial controllers, test equipment, and prototyping where modern CPLDs are not required. When designing with the EP610DC-15, ensure the programming algorithm and JEDEC file are compatible with the 610 macrocell architecture. The CDIP-24 ceramic package has a transparent quartz window for UV erasure; protect the window from ambient light with opaque labels after programming to prevent data corruption. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

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EP610DC-20 - 24-Pin CMOS UV PLD, 22ns Delay | Altera/Intel
EP610DC-20

EP610DC-20 - 24-Pin CMOS UV PLD, 22ns Delay | Altera/Intel

The Altera EP610DC-20 is a CMOS UV-erasable Programmable Logic Device (PLD/EPLD) from the Classic EP610 family, featuring 16 macrocells, 4 dedicated inputs, 16 I/O pins, and a 22 ns propagation delay (the '20' speed grade). Housed in a 24-pin Ceramic Dual In-line Package (CDIP-24), the EP610DC-20 implements combinational and registered logic through Altera's sum-of-products (sum-of-products) AND/OR architecture with 160 product terms, providing a maximum toggle frequency of 55.6 MHz when used in registered or counter modes. The device operates from a single 5 V supply (VCC = 4.75 V to 5.25 V) over the commercial 0 °C to 70 °C temperature range. A Programmable Logic Device (PLD) is a digital integrated circuit whose internal logic and interconnect can be configured by the end user after manufacture, bridging the gap between discrete 74-series logic gates and fixed-function ASICs. The EP610 family is a 'Classic' generation EPLD fabricated on Altera's UV-erasable CMOS process, meaning the configuration is stored in floating-gate memory cells that can be cleared with approximately 20 minutes of UV-C exposure through the package window (the ceramic CDIP body provides this window). In the modern taxonomy, PLDs sit under the broader umbrella of programmable logic devices -> EPLD -> Classic UV-PLD -> semiconductor. They are positioned above simple PALs (smaller arrays, no registered outputs) and below modern CPLDs and FPGAs (larger logic capacity, in-system programmability, SRAM or flash-based configuration). Key features of the EP610DC-20 include 16 macrocells with selectable D/T/JK flip-flops, a single 5 V supply, a pin-compatible speed-grade family with 20/15/10 ns tPD options (EP610DC-20/DC-15/DC-10), 160 product terms (also called 'p-terms'), and a dedicated clock/clear architecture. Each macrocell drives one of the 16 bidirectional I/O pins, and 4 pins are dedicated inputs only, giving a usable logic capacity of approximately 24 pins total. The device is supported by the legacy Altera MAX+PLUS II development environment (and MAX II), which compiles AHDL, VHDL, or schematic designs into the JEDEC fuse-map for programming. The architecture is a classic AND-OR-NOT PLA feeding a configurable output macrocell. Each macrocell has a programmable output polarity, a tri-state buffer, and an optional flip-flop (D, T, JK, or latch). Product-term allocation is fixed (no expander chain), which simplifies timing analysis: all signals reach the OR array with a single tPD delay. This deterministic timing is one of the main reasons EPLDs were used in place of discrete TTL or early FPGAs in the 1980s and 1990s for glue logic, address decoding, and state machines. Typical applications include legacy bus-interface glue logic (e.g., address decoding for ISA, VME, or STD-bus cards), state-machine controllers for industrial equipment, register and counter arrays replacing multiple 74LS/74F packages, and pin-compatible retrofits for systems that were originally designed around the EP610 family. The 24-pin CDIP-24 ceramic package makes it especially suitable for military, aerospace, and high-reliability programs where a UV-clearable hermetic device is preferred over plastic UV-windowless plastic PLDs. When designing with this part, note that the configuration is volatile until programmed and that the ceramic DIP provides a quartz window for UV erasure. Programming requires an Altera-compatible parallel programmer (e.g., LogiCade, BP Microsystems) since modern USB programmers do not target this legacy family. Decoupling requires 0.1 µF ceramic capacitors on every VCC pin, plus a bulk tantalum or electrolytic cap on the board-level 5 V rail. This page synthesizes distributor pricing, drop-in alternative MPNs (including same-family EP610DC-15 and EP610DC-10), legacy-programming guidance, and practical design notes not found in a single manufacturer datasheet.

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EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25

EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester

The Rochester Electronics EP610DC-25 is a high-performance 16-macrocell Classic EPLD from the Altera Classic EPLD family, originally manufactured by Altera (now Intel PSG) and presently authorized for continued production and distribution by Rochester Electronics as a long-life-cycle partner. Per the EP610 datasheet family specification, the EP610DC-25 integrates 300 gates, 16 macrocells, and 22 I/O pins in a 24-pin ceramic DIP (CDIP-24) through-hole package, with a worst-case pin-to-pin propagation delay (tPD) of 25 ns and pipelined data rates reaching up to 100 MHz. A Classic EPLD (Erasable Programmable Logic Device) is a type of early-generation programmable logic IC that combines the high integration of a PLD with the erasable, reprogrammable nature of UV-erasable CMOS logic. EPLDs sit within the broader programmable logic hierarchy: PLD -> CPLD (Complex PLD) / EPLD -> FPGA. The Classic family targets glue-logic, decode, and state-machine applications where a small number of logic equations must be implemented with deterministic, TTL-equivalent timing. Key specifications include a maximum tPD of 25 ns, 22 user I/O pins, 4 dedicated input pins (24 pins total minus VCC/GND), 16 macrocells, 300 equivalent gates, an internal supply voltage of 4.75 V to 5.25 V (5 V nominal), and a commercial operating temperature range of 0 C to +70 C. The -DC- suffix indicates the ceramic DIP package, while the -25 speed grade indicates the 25 ns tPD timing bin. Architecturally, the EP610 uses a sum-of-products AND/OR array feeding 16 output macrocells with programmable output polarity and feedback paths, allowing combinatorial and registered logic to be implemented in a single device. The CMOS EPROM technology gives the part zero standby current when not being read, while the macrocell flip-flops provide synchronous register-based state-machine support. With pipelined data rates to 100 MHz, the EP610DC-25 is suitable for high-speed decoder, address-decode, and bus-arbitration roles in legacy 5 V systems. Typical applications include bus decode and address decoding in 5 V microprocessor systems, glue logic in industrial controllers, state-machine controllers for instrumentation, and pin-compatible logic replacement for legacy designs where the original Altera Classic EPLD must be renewed. The 24-pin DIP form factor is also favored for breadboarding and educational platforms. When designing with the EP610DC-25, ensure the design is implemented in legacy Altera Classic EPLD design tools or compatible JEDEC fuse-map programming software, as modern Quartus software does not support the Classic family.

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EP610DC-30 - Classic EPLD, 16 Macrocells, 30ns | Altera
EP610DC-30

EP610DC-30 - Classic EPLD, 16 Macrocells, 30ns | Altera

The Altera EP610DC-30 is a Classic EPLD (Erasable Programmable Logic Device) featuring 16 macrocells and 300 usable gates, packaged in a 24-pin ceramic DIP (CERDIP) form factor with a 30 ns propagation delay grade. As a member of the EP610 family, this device implements high-performance CMOS EPROM-based programmable logic with pipelined data rates of up to 100 MHz, targeting legacy glue-logic and state-machine replacement tasks in industrial, telecommunications, and aerospace systems. A Classic EPLD is an early-generation programmable logic device that uses EPROM cells to store the configuration. In the broader taxonomy, the EP610DC-30 sits inside the PLD (Programmable Logic Device) family, which is a subset of programmable logic alongside CPLDs and FPGAs. EPLDs were widely adopted in the late 1980s and 1990s as a means of replacing discrete 74-series TTL/MSI glue logic, integrating state machines, address decoders, bus arbiters, and counter/timer functions into a single non-volatile, one-time-programmable (windowed-erasable UV) IC. The Classic device family preceded the MAX series and offers pin-to-pin compatibility across the EP610 and EP910 lines. Key features include 16 macrocells organized in 4 Logic Expanders, 16 dedicated input pins, and 16 I/O pins with output enable control, plus a programmable clock with global and per-macrocell options. The EP610DC-30 supports a maximum toggle frequency of 100 MHz in pipelined mode, delivers a tPD (pin-to-pin propagation delay) of 30 ns in commercial temperature grade, and offers both registered and combinatorial output modes. The device also features a synchronous preset and asynchronous clear network, plus a security bit to protect proprietary designs after programming. Architecturally, the EP610DC-30 uses a sum-of-products (AND-OR-XOR) PLA-like structure with a global interconnect that routes the 16 inputs and 16 feedback paths into 4 Logic Expanders, each producing 4 product terms per macrocell. The JEDEC-standard 24-pin ceramic DIP package supports through-hole mounting, which is typical for legacy and aerospace applications where socketed, field-replaceable logic remains preferred. Typical applications include TTL/MSI glue-logic replacement in industrial controllers, address decoding in 8-bit and 16-bit microprocessor systems (such as 8086 and 68000 bus interfaces), state-machine implementations in telecom and instrumentation, and aerospace/avionics systems requiring ceramic-package reliability. Designers transitioning from 74LS/74ALS logic to a programmable equivalent often select this part for its predictable timing and EPROM non-volatility. When designing with the EP610DC-30, note that ceramic DIP packages require through-hole PCB footprints and are not compatible with modern surface-mount assembly processes. Programming requires a UV-erasable window (no in-system programmability), and design entry uses legacy tools such as Altera MAX+PLUS II or the older A+PLUS environment. Designers should verify second-source availability (Rochester Electronics and Intel/Altera continue to manufacture this part) before committing to new designs.

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EP610DC-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
EP610DC-35

EP610DC-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera

The Altera EP610DC-35 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 24-pin windowed CERDIP (CDIP-24) through-hole package. It belongs to the Altera Classic device family and is rated for a 35ns pin-to-pin propagation delay (the "-35" speed grade), with pipelined data rates reaching up to 100 MHz. The device provides 300 usable gates, 16 macrocells, and operates from a single 5V supply. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays with a programmable interconnect. CPLDs sit in the broader hierarchy of programmable logic: programmable logic device (PLD) -> CPLD -> programmable logic -> semiconductor. They are commonly used as "glue logic" to replace discrete 74-series TTL gates, state machines, address decoding, and bus interfacing in designs where an FPGA would be over-specified. The EP610DC-35 features a UV-erasable quartz windowed CERDIP package, allowing the device to be erased with ultraviolet light and re-programmed many times - ideal for prototyping and design iteration. The CMOS Classic architecture provides bipolar-compatible speed at CMOS power levels, with deterministic timing that simplifies static timing analysis. Macrocell flip-flops and product-term sharing support both combinatorial and registered logic functions. Typical applications include address decoding and interrupt generation in 8-bit and 16-bit microprocessor systems, bus arbitration and glue logic in industrial controller boards, state-machine-based peripheral controllers, and replacement of multiple discrete PAL/TTL packages. The 5V single-supply operation and 24-pin DIP form factor are convenient for legacy and through-hole designs. When designing with the EP610DC-35, engineers should note that the part is mature/legacy silicon and is supplied today through Rochester Electronics as an authorized Altera/Intel foundry partner. Lead time and pricing should be confirmed at order entry. Use the Altera MAX+plus II or classic Altera programming tools with a compatible parallel-port programmer for device configuration. This page synthesizes distributor pricing, authorized stocking-channel information, drop-in alternatives, and practical design notes for the EP610DC-35 - information not consolidated in the original Altera datasheet alone.

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EP610DC15 - 16-Macrocell Classic EPLD, 15ns tPD | Intel / Altera
EP610DC15

EP610DC15 - 16-Macrocell Classic EPLD, 15ns tPD | Intel / Altera

The Intel / Altera EP610DC15 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, offering a 15 ns propagation delay and pipelined data rates up to 100 MHz in a 24-pin ceramic DIP (CDIP) windowed package. It features PAL-type architecture with 20 inputs, 16 I/O lines, and 160 product terms for flexible combinatorial and registered logic implementation, operating from a single 4.75 V to 5.25 V supply. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits in the broader taxonomy of programmable logic devices (PLDs), which also include PALs, GALs, CPLDs, and FPGAs. EPLDs use EPROM or EEPROM cells to store the configuration, allowing them to be re-programmed and reused across design iterations. The Classic EPLD family preceded the modern MAX series and was historically used for glue logic, address decoding, state machines, and bus interfacing before FPGAs became cost-competitive. Key features of the EP610DC15 include 71.4 MHz maximum clock frequency, CMOS technology with low power consumption, in-system erasability via the ceramic-windowed package, and JEDEC-standard pinout for socket compatibility with EP610DC-10/15/20/25/30/35 speed grades. The device supports both combinatorial and registered outputs with user-configurable macrocell flip-flops. The EP610 architecture uses a global bus that distributes product terms to 16 macrocells, each containing a flip-flop and output enable control. This centralized interconnect provides predictable timing with fixed propagation delay, making it well-suited for asynchronous and synchronous logic replacement where deterministic behavior is required. Typical applications include legacy industrial control replacement, address decoding for 8086/68000 microprocessor systems, state machine implementation, bus arbitration logic, and educational lab platforms. The wide supply tolerance and TTL-compatible I/O simplify integration with 5 V logic families. When designing with this device, note that the EP610DC-15 is an NRND/EOL part. New designs should consider the Altera MAX II or MAX V CPLD families, which offer higher density, lower power, and modern packages. The CDIP-24 windowed package requires UV erasure for reprogramming.

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EP610DC35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
EP610DC35

EP610DC35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera

The Altera EP610DC35 (also written EP610DC-35) is a 16-macrocell Classic EPLD from Altera's Classic EPLD family, housed in a 24-pin ceramic DIP (CDIP-24) through-hole package with a 35ns propagation delay grade. It provides 300 usable gates and pipelined data rates of up to 100 MHz, delivering non-volatile, deterministic logic integration for legacy industrial and military designs. Classic EPLDs (Erasable Programmable Logic Devices) are ultraviolet-erasable, CMOS-based programmable logic devices that pre-date modern CPLDs and FPGAs. They belong to the broader category of programmable logic devices (PLDs), which also include SPLDs, CPLDs, and FPGAs. EP610-series devices are organized as a single AND/OR logic block feeding a fixed-output macrocell array, providing predictable timing suitable for address decoding, bus interfacing, and glue-logic replacement in 5V systems. Key features include 16 macrocells, 300 gates of usable logic, a maximum propagation delay of 35ns (tPD), and a 5V single-supply operation with 5V-tolerant I/O. The EP610DC35 is windowed (ceramic DIP with quartz erase window) and is one of the speed grades in the EP610 family, distinguished from -10, -15, -20, -25, and -30 grades by its 35ns timing. The device supports both combinational and registered logic with pin-feedback architecture and is in-system programmable via Altera's classic programming algorithm. Architecturally, the EP610 uses Altera's Classic EPLD macrocell with sum-of-products logic feeding programmable flip-flops, plus a global clock network and JTAG-free programming interface. The 5V CMOS EPROM technology yields high noise immunity and latch-up resistance, making it well suited to industrial control boards, avionics retrofits, and 5V legacy embedded platforms where modern 3.3V/2.5V PLDs are not pin-compatible replacements. Typical applications include 5V bus interface glue logic, address decoding for M68k and x86 embedded systems, state-machine controllers, peripheral chip replacement, and military/aerospace systems requiring 5V tolerance and high reliability. The CDIP-24 ceramic package offers extended temperature performance and is preferred over plastic DIPs in aerospace and defense systems. When designing with the EP610DC35, note that it is programmed with an Altera legacy programmer (e.g., PLDLMax or compatible) and cannot be re-programmed in-system via JTAG. Designs should also budget the 35ns tPD carefully when interfacing to high-speed buses; for faster speeds the EP610DC-25 or EP610DC-20 grades should be considered.

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EP610DI-25 - 25ns Classic EPLD, 16 Macrocells | Altera (Intel)
EP610DI-25

EP610DI-25 - 25ns Classic EPLD, 16 Macrocells | Altera (Intel)

The Altera (Intel) EP610DI-25 is a 25 ns propagation-delay Classic EPLD (Erasable Programmable Logic Device) featuring 16 macrocells, 16 bidirectional I/O lines, and 4 dedicated inputs, housed in a 24-pin ceramic glass-sealed DIP (R-GDIP-T24) package. The "I" suffix denotes the industrial (ceramic) temperature variant and the "25" indicates the 25 ns tPD speed grade, while the "DI" package code identifies the ceramic DIP through-hole form factor. A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable, CMOS-based programmable logic device belonging to the programmable logic device (PLD) family, which sits hierarchically between discrete logic gates (lowest density) and modern FPGAs (highest density) in the logic integration taxonomy: discrete logic -> PLD -> CPLD -> FPGA -> SoC FPGA. EPLDs use a sum-of-products (AND-OR) PLA-style architecture with a non-volatile EPROM cell, allowing designers to implement glue logic and state machines that retain configuration after power removal. The EP610 is one of Altera's foundational Classic EPLD parts that helped establish the PLD market. Key features include 25 ns pin-to-pin propagation delay, pipelined data rates up to 100 MHz, 16 macrocells with user-configurable D/T/JK flip-flops, 16 I/O pins, 4 dedicated inputs, and EPROM-based non-volatile configuration. The device offers predictable, deterministic timing identical for every logic path, simplifying static timing analysis compared to SRAM-based FPGAs. A single 5 V power supply and a standard JEDEC programming interface simplify design-in. The EP610DI-25 uses an EPROM-cell CMOS architecture with a programmable AND/OR array. Logic is implemented as sum-of-products expressions with optional registered output via the macrocell flip-flop. This architecture trades flexibility for predictability, making the part well-suited to bus decoding, address decoding, state machines, and custom peripheral interfaces in legacy 5 V systems. Typical applications include TTL/CMOS logic integration, bus decoding and address mapping in 5 V microprocessor systems, peripheral interface glue logic, state-machine controllers, and legacy industrial control replacement. The ceramic DIP package supports through-hole assembly typical of older industrial, military, and aerospace equipment still in service. When designing with this part, note that the device is one-time-programmable only via UV erasure (windowed package), so designers must budget an EPROM eraser step into the prototyping workflow. Programming requires a compatible device programmer supporting the Classic EPLD family. Modern 3.3 V systems require level shifters to interface this 5 V part. This page synthesizes distributor pricing, drop-in replacement MPNs, and design considerations not found in the original 1990s datasheet, enabling accurate sourcing for long-lifecycle equipment support.

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EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30

EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics

The Rochester Electronics EP610DI-30 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 24-pin ceramic DIP (CERDIP-24) windowed package, with a propagation delay of 30 ns and a pipelined data rate of up to 100 MHz. The UV-erasable windowed CERDIP allows the device to be erased with ultraviolet light and reprogrammed in-system, supporting iterative development and field upgrades typical of the original Altera Classic EPLD family. What is a Classic EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that sits in the hierarchy between discrete PAL/GAL devices and modern FPGAs/CPLDs. Classic EPLDs use EPROM/EEPROM cells to store AND/OR logic terms and are typically programmed once (one-time-programmable, OTP) or with UV erasure (windowed packages). They fill the role of glue logic, state machines, and address decoding in systems where modern FPGAs would be over-spec and discrete logic would be too bulky. The EP610 belongs to the first wave of commercially successful EPLDs, offering 16 macrocells and reasonable speed at low power for the era. Key features of the EP610DI-30 include 16 macrocells of programmable logic, 30 ns propagation delay (commercial -30 speed grade), a pipelined clock rate of up to 100 MHz, and CMOS technology for low standby power. The device operates from a single 5 V supply and is pin-compatible with the rest of the EP610 family, allowing easy migration across speed grades (tPD = 15, 20, 25, 30 ns) and across package options (DIP, SOIC, ceramic DIP). The architecture is based on a programmable AND/OR array feeding 16 output macrocells with user-configurable registers, I/O direction, and feedback paths. Programming is performed via the standard Altera EP610 programming algorithm through dedicated programming pins on the device. The windowed CERDIP-24 package supports UV erasure for lab development, while the plastic DIP variant is intended for one-time-programmed production. Typical applications include glue logic replacement, address decoding for microprocessor and microcontroller systems, state machines and sequencers, bus interface logic, custom peripheral controllers, and legacy industrial control systems. The EP610 is also widely used in educational settings and as a low-cost entry point for learning programmable logic design. When designing with the EP610DI-30, note that the -30 speed grade is one of the slower variants; for higher throughput consider the EP610DC-15 or EP610DC-20. The CERDIP-24 package consumes substantial board area and the quartz window is sensitive to scratches - cover the window with opaque label after programming to prevent accidental UV erasure. This page synthesizes distributor pricing, package/die equivalents in the EP610 family, and practical design notes not aggregated on the manufacturer datasheet.

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EP610DI-30N - Classic 16-Macrocell EPLD, 30ns CDIP-24 | Altera
EP610DI-30N

EP610DI-30N - Classic 16-Macrocell EPLD, 30ns CDIP-24 | Altera

The Altera EP610DI-30N is a Classic-family Erasable Programmable Logic Device (EPLD) from the EP610 series, offering 16 macrocells, 300 usable gates, and a 30 ns pin-to-pin propagation delay in a 24-pin ceramic DIP (CDIP) windowed package. Operating from a single 5 V supply, it provides up to 33.3 MHz system clock rates and pipelined data rates reaching 100 MHz, making it well-suited for glue-logic, bus decoding, and state-machine replacement in legacy industrial designs. The 'I' temperature range (-40°C to +85°C) and the 'N' windowed ceramic DIP suffix enable in-system reprogramming via UV erasure, a hallmark of the Classic EPLD family used through the 1990s. An EPLD (Erasable Programmable Logic Device) is a type of non-volatile programmable logic IC that predates modern CPLDs and FPGAs. Positioned in the taxonomy as EPLD -> CPLD -> programmable logic -> logic IC, the EP610 family pioneered the AND/OR fixed-architecture with sum-of-products logic feeding an output macrocell, providing predictable, deterministic timing that rivals discrete TTL glue logic but with much higher integration density. Key features include 16 macrocells, each with programmable I/O polarity, output enable, and feedback, 24 dedicated input pins, a 5 V ±5% supply, and TTL-compatible inputs/outputs. The EP610DI-30N ships as a UV-erasable windowed ceramic DIP, allowing engineers to erase and reprogram the device during development cycles - a significant advantage over one-time-programmable (OTP) plastic-DIP variants. According to the Rochester Electronics datasheet reference, the device is qualified for industrial-temperature operation. The architecture uses a CMOS AND array feeding an OR array into output macrocells, providing predictable tPD timing independent of routing. The 30 ns tPD (suffix -30) places the EP610DI-30N in the mid-speed tier of the Classic EPLD family; faster -25 and -20 grades exist for more demanding glue-logic applications, while slower -35 and -40 grades serve cost-sensitive designs. Typical applications include 5 V bus-interface decoding (e.g., address decoding in 8086/68k/Motorola microprocessor systems), state-machine replacement for discrete 74LS glue logic, custom peripheral controllers in legacy industrial equipment, and prototyping logic for designs that later migrate to a pin-compatible OTP or masked variant. The device is also commonly used to repair or extend legacy boards originally built with the plastic-DIP OTP EP610PC variant. When designing with this device, place 0.1 µF decoupling capacitors within 50 mm of each VCC pin and route ground returns directly to the system ground plane. Note that the windowed ceramic package adds significant vertical clearance (~6 mm) versus plastic DIP - account for this in mechanical enclosures. The EP610DI-30N is widely available through authorized distributors like Rochester Electronics as a long-lifecycle sustainment part for legacy systems. This page consolidates distributor pricing, drop-in same-family alternatives (EP610DI-25, EP610DI-20, EP610PC variants), and practical design notes beyond the bare datasheet, helping engineers source a pin-compatible EPLD for legacy 5 V logic designs.

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EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35

EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera

The Intel / Altera EP610DI-35 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from Altera's EP610 family, delivering a propagation delay of 35 ns (tpd) and housed in a 24-pin ceramic DIP (CDIP-24) package. It contains 300 usable gates, 16 macrocells interconnected by a global bus, and 160 product terms, with 16 bidirectional I/O lines and 20 total inputs including 4 dedicated clock/control inputs. The device operates from a single 5 V supply and supports pipelined data rates up to 100 MHz internally, with a maximum external toggle frequency of 28.6 MHz. A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable, CMOS-based programmable logic device that predates modern CPLDs and FPGAs, used to implement random-logic glue functions, state machines, and address decoding. EP610 sits in the programmable logic hierarchy: programmable logic device (PLD) > EPLD > Classic EPLD, with macrocell-based architecture serving as a direct replacement for multiple discrete PAL/GAL devices in legacy designs. Key features include CMOS technology for low power consumption, in-system erasability via UV exposure window, registered or combinational macrocell configuration, and synchronous/asynchronous clocking options. The device provides architectural flexibility through output polarity programming and configurable feedback paths on every macrocell. Architecturally, EP610 uses a sum-of-products PLA structure feeding a programmable output macrocell array. Its 16 I/O pins share the global bus, while the 4 dedicated inputs handle clock and control functions. The 35 ns propagation delay positions EP610DI-35 as the mid-speed variant of the family, suitable for applications below 28 MHz toggle rates. Typical applications include legacy industrial control logic, address decoding for 8-bit and 16-bit microprocessor systems, bus interfacing glue logic, state-machine replacement for multiple TTL packages, and educational/prototyping platforms. The CDIP-24 ceramic package also makes it suitable for military and aerospace programs that still require through-hole, ceramic-bodied programmable logic. When designing with EP610DI-35, note that it requires a 5 V supply and UV erasure for reprogramming; a modern Lattice or Xilinx CPLD is a faster, in-system-programmable alternative for new designs. Verify the 24-pin CDIP footprint matches your PCB land pattern before selecting it as a drop-in replacement. This page synthesizes distributor pricing, drop-in Classic EPLD alternatives, and practical design notes not found in the original Altera datasheet.

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EP610DM-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
EP610DM-35

EP610DM-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera

The Altera EP610DM-35 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the original Altera Classic family, delivered in a 24-pin ceramic DIP (CDIP) windowed package with a 35 ns propagation delay. It is a UV-erasable, CMOS, PAL-type programmable logic device with 300 gates, 16 macrocells, and a pipelined data-rate capability of up to 100 MHz. A Classic EPLD is a member of the early programmable logic device (PLD) family that preceded modern CPLDs and FPGAs. EPLDs provide sum-of-products logic, macrocell-based I/O, and non-volatile (UV-erasable) configuration in a small pin-count DIP, ideal for glue logic, address decoding, bus interfacing, and state-machine replacement in legacy industrial, telecom, and military systems. The EP610DM-35 sits within the broader taxonomy of programmable logic: PLD -> EPLD -> Classic EPLD -> CMOS PAL-type EPLD. Key features include 24 dedicated input pins, 16 bidirectional I/O macrocells, a 35 ns pin-to-pin propagation delay (tPD), a 100 MHz pipelined fMAX, and a single 5 V supply. The 'D' suffix denotes the ceramic DIP package with a quartz window for UV erasure; the 'M' grade indicates military temperature range (-55C to +125C). The device is reprogrammable, JTAG-free, and uses Altera's MAX+plus II or classic Altera development tools for fitting. Architecturally, the EP610DM-35 uses a programmable AND/OR array feeding 16 output macrocells with user-configurable flip-flops. Each macrocell can be set to combinatorial or registered output with dedicated feedback, allowing state machines, counters, and registered decoders. The Classic architecture is non-volatile, making the part an attractive choice for systems that must boot into a known logic state without external configuration memory. Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding in 80C86/80C88 and Motorola 68000 microprocessor systems, MIL-STD-1553 and ARINC-429 interface adapters, military/aerospace digital subsystems, and replacement of discrete TTL/CMOS glue in long-lifecycle equipment where modernization is impractical. When designing with this device, ensure that the input rise/fall times meet the 5 V CMOS thresholds (typically <100 ns) to avoid spurious transitions, and budget sufficient tCO (clock-to-output) and tSU (setup-time) margins in synchronous paths. The 35 ns grade is appropriate for sub-30 MHz system clocks; for faster designs, select the EP610DI-25 (25 ns) or EP610DM-25 equivalent. This page synthesizes distributor stock data, same-package EPLD alternatives, and design notes not found in the original Altera datasheet, supporting long-tail lifecycle maintenance for this mature Classic EPLD part.

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EP610DM/883B - 16-Macrocell Classic EPLD, 100MHz, CDIP-24 | Intel
EP610DM/883B

EP610DM/883B - 16-Macrocell Classic EPLD, 100MHz, CDIP-24 | Intel

The Intel (formerly Altera) EP610DM/883B is a high-performance, 16-macrocell Classic Erasable Programmable Logic Device (EPLD) in a 24-pin Ceramic DIP (CDIP) package, qualified to MIL-STD-883 Class B for military and aerospace applications. Pipelined data rates reach up to 100 MHz, with 24 dedicated input pins and 16 output macrocells organized into a programmable AND/OR architecture that replaces multiple SSI/MSI logic packages. A Classic EPLD is an early-generation programmable logic device sitting in the broader taxonomy of programmable logic: PAL -> PLA -> EPLD -> CPLD -> FPGA -> SoC FPGA. Classic EPLDs from the EP610 family use UV-erasable CMOS EPROM cells to store the logic configuration, providing non-volatile behavior without an external configuration memory. The EP610DM/883B is intended for glue-logic, address decoding, state-machine, and bus-interface replacement tasks where pin-count, deterministic timing, and military-grade reliability are required. Key features include 16 macrocells, 24 pins total, dedicated input register paths, and a tPD propagation delay on the order of 25 ns (commercial grade). The /883B suffix indicates full MIL-STD-883 Class B screening, covering extended temperature range, burn-in, and 100% electrical test at temperature corners. The CDIP-24 ceramic package offers hermetic sealing suitable for harsh-environment deployments. The architecture implements a sum-of-products AND/OR array feeding 16 flip-flop-backed output macrocells, with a synchronous clock network and asynchronous clear/preset support on every macrocell. This structure maps cleanly to state machines, decoder logic, and bus-arbitration functions, replacing multiple 74LS/74F TTL packages with one programmable device and reducing board area and BOM count. Typical applications include military and avionics systems, industrial control, legacy replacement of 74-series glue logic, address decoding in VME/VXI backplanes, and radiation-tolerant logic subsystems. The /883B screening makes it suitable for programs requiring MIL-PRF-38535 qualified parts or DESC-approved sources. When designing with this device, note that programming requires a classic EPROM-based programmer (not a JTAG interface). Logic fitting must be verified against the 16-macrocell resource limit; larger designs require migration to MAX series or modern CPLD families. Always derate switching speed at temperature extremes per MIL-STD-883 curves.

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EP610IDC-10 - 16-Macrocell Classic EPLD, 10ns, CDIP-24 | Altera
EP610IDC-10

EP610IDC-10 - 16-Macrocell Classic EPLD, 10ns, CDIP-24 | Altera

The Altera EP610IDC-10 is a Classic-series Erasable Programmable Logic Device (EPLD) delivering 300 usable gates, 16 macrocells, and a 10 ns pin-to-pin logic delay in a 24-pin ceramic DIP (CDIP) package. It belongs to the original Altera Classic EPLD family, fabricated on advanced CMOS technology, with a 100 MHz maximum counter frequency and 5V TTL-compatible I/O. A Classic EPLD is a non-volatile programmable logic device that combines the density of a small PLD with the speed and pin-count flexibility of early FPGAs. It sits within the broader hierarchy of programmable logic devices (PLD), between simple PAL/GAL arrays and full FPGAs. EPLDs use a sum-of-products architecture with user-programmable AND/OR planes and a fixed, deterministic interconnect, which makes them ideal for fast control logic, address decoding, and state machines where predictable timing is more important than raw gate density. Key features of the EP610IDC-10 include 16 macrocells, 4 dedicated inputs plus 20 I/O pins, an on-chip programmable interconnect, support for 100% TTL emulation, and an integrated test circuitry that allows AC specification verification during production. The device is in-system programmable via the Altera MAX+PLUS II development environment and supports JTAG-style boundary-scan testing on selected package variants. The Classic architecture is macrocell-based: each macrocell contains a programmable flip-flop, configurable I/O, and shared product-term logic that feeds the AND/OR array. Compared with one-time-programmable (OTP) PALs, the EP610IDC-10 is windowed ceramic and therefore erasable with UV light, making it suitable for development and low-volume prototyping rather than high-volume production. Typical applications include high-speed address decoding for 8086/80286-era microprocessor systems, bus interface logic, glue logic in industrial controllers, state machines for instrumentation, and 5V TTL glue-logic replacement. Designers also use Classic EPLDs to consolidate multiple discrete 74LS/74F logic packages into a single programmable device for legacy system refresh. A key design consideration is the 5V supply requirement: the EP610IDC-10 is not 5V-tolerant in a mixed-voltage system, so any 3.3V signals must be level-shifted. The CDIP-24 ceramic windowed package requires a UV eraser socket for reprogramming, so production volumes should migrate to the plastic OTP (one-time-programmable) EP610PC-10 variant. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers evaluate EPLD alternatives for legacy design maintenance and obsolescence avoidance.

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EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
EP610IDC-15

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

The Intel EP610IDC-15 is a 16-macrocell Classic EPLD from the Altera Classic device family, fabricated in CMOS and housed in a 24-pin ceramic dual in-line package (CerDIP) with a 15 ns propagation delay. It provides 300 usable gates, a 66 MHz maximum operating frequency, and 5V nominal supply operation across the commercial 0C to +70C temperature range. The device implements UV-erasable / OTP logic for in-system prototyping and is supported by the MAX+PLUS II development environment. A Classic EPLD (Erasable Programmable Logic Device) is a member of the SPLD/CPLD hierarchy of programmable logic devices. Architecturally, an EPLD sits between simple PAL/GAL SPLDs and modern high-density CPLDs/FPGAs, offering non-volatile, deterministic combinatorial-and-sequential logic blocks (macrocells) with pin-to-pin timing guarantees. In the broader taxonomy: programmable logic -> SPLD/EPLD -> Classic EPLD -> macrocell array. EPLDs are valued for low-power, deterministic, single-chip glue-logic replacement of discrete 74LS/74HC TTL. Key features of the EP610IDC-15 include 16 macrocells with user-programmable I/O, 24 dedicated input pins, an internal logic-test mode for AC verification during production, pin-to-pin delay of 15 ns, and CMOS standby current well below bipolar predecessors. The CerDIP-24 ceramic package provides hermeticity for legacy industrial and military programs that demand through-hole reliability and DIP-handling compatibility. The architecture is built on a CMOS EPROM cell array driving an AND/OR macrocell fabric with programmable registers. Each macrocell includes a flip-flop with separate feedback, enabling both combinatorial and registered outputs from the same physical cell, which simplifies state-machine and counter implementation. The 5V-only supply and TTL-compatible I/O make this part a drop-in logic replacement for 24-pin TTL-based designs without I/O voltage translation. Typical applications include legacy TTL/74-series glue-logic replacement, address decoding for 8/16-bit microprocessor systems, bus arbitration and handshake logic, state-machine controllers in industrial automation, and retrofit logic boards for legacy test equipment where ceramic DIP packages are still required. Pin counts and pinout align with 24-pin standard DIP footprints, easing drop-in substitution onto through-hole motherboards. When designing with the EP610IDC-15, use a programming current of 11.0 mA typical (per Classic family datasheet), place a 0.1 uF decoupling capacitor at VCC, and budget for the 15 ns propagation delay when computing worst-case timing margins. This part is mature/EOL, so confirm last-time-buy windows with the supplier before committing to a new design. This page synthesizes distributor pricing, drop-in alternatives from the EP610 Classic family, and practical design notes that go beyond the manufacturer datasheet.

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EP610ILC-10 - Classic EPLD, 16 Macrocells, 10ns tPD, PLCC-28 | Altera
EP610ILC-10

EP610ILC-10 - Classic EPLD, 16 Macrocells, 10ns tPD, PLCC-28 | Altera

The Altera EP610ILC-10 is a 5 V, UV-erasable/OTP Classic-series Erasable Programmable Logic Device (EPLD) housed in a 28-pin plastic J-lead chip carrier (PLCC) package, providing 300 usable gates and 16 macrocells at pin-to-pin logic delays as low as 10 ns and counter frequencies up to 100 MHz. The device implements a PAL-type architecture with 16 dedicated input pins and 16 I/O macrocell outputs, giving designers a glue-logic alternative to small PAL/GAL devices with deterministic, non-volatile 5 V silicon. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the integration density of early PLDs with erasable EPROM-style configuration memory; in the broader taxonomy EPLD -> PLD -> programmable logic -> digital IC, the EP610 sits at the low-density end typically used to replace discrete TTL/CMOS glue logic, state machines, address decoders, and bus-interface functions. The Classic family provides pin-to-pin delays of 10-25 ns and supports counter frequencies up to 100 MHz, making it suitable for synchronous control logic in industrial and embedded systems. Key features of the EP610ILC-10 include 160 product terms, 4 dedicated inputs, 16 I/O pins, and a 5 V single-supply operation; the -10 speed grade delivers 10 ns tPD and 100 MHz fCNT, allowing the device to be clocked at full speed without metastability issues typical of slower PALs. The macrocell architecture supports both registered and combinatorial outputs with feedback, enabling efficient state-machine implementation. The PLCC-28 package uses J-leads suitable for socketed programming and field replacement, which is important for legacy and MIL-spec applications. Typical applications include address decoding in 8086/68000 microprocessor systems, glue logic in VMEbus/ISA backplanes, state machines in industrial controllers, and bus arbitration logic in legacy embedded systems. The 5 V supply and TTL-compatible I/O make the EP610 directly compatible with bipolar and CMOS 5 V logic families including 74LS, 74HC, and 74F series. When designing with the EP610ILC-10, ensure that input rise/fall times remain below the datasheet limit to avoid AC noise issues, and provide proper decoupling with 0.1 uF capacitors on each VCC pin. Because the EP610 is a legacy part with limited current production, engineers should verify lifecycle status with the distributor before committing to new designs and consider pin-compatible successors such as the EP610ILC-12 or EP910 for higher gate counts.

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EP610ILC-25 - Classic EPLD 300 Gates 16 Macrocells 25ns | Altera
EP610ILC-25

EP610ILC-25 - Classic EPLD 300 Gates 16 Macrocells 25ns | Altera

The Altera EP610ILC-25 is a 25ns Classic EPLD (Erasable Programmable Logic Device) from Altera's EP610 series, delivering 300 usable gates, 16 macrocells, and 40 MHz maximum operating frequency in a 28-pin PLCC package. It is a CMOS, PAL-type Electrically Erasable Programmable Logic Device (EEPLD) offering 160 product terms and flexible macrocell output architecture for legacy 5V logic designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays with a central interconnect, allowing engineers to implement custom glue logic, state machines, and bus interface functions without the cost of an ASIC. The EP610 belongs to Altera's Classic EPLD family — the early 5V generation that pre-dated the MAX 7000 series and now sits firmly in the legacy/last-time-buy segment of the Altera (now Intel PSG) catalog. Key features of the EP610ILC-25 include 4 dedicated inputs and 16 bidirectional I/O pins (20 total inputs), 16 macrocells with configurable D/T/JK/SR flip-flop options, 160 product terms for sum-of-products logic, and a 25ns pin-to-pin propagation delay that supports a 40 MHz internal fMAX. The device is electrically erasable, enabling in-system reprogramming during development and field upgrades. It operates from a single 5V supply (4.75V to 5.25V) with commercial temperature range of 0C to +70C. The EP610ILC-25 architecture pairs a programmable AND array feeding a fixed OR array into 16 macrocells, each capable of registered or combinatorial output with selectable feedback paths. The JTAG-less, 5V-only design philosophy makes it a straightforward drop-in for legacy PAL/GAL replacement designs and for engineers migrating older prototype boards into a single, denser, erasable part. Typical applications include legacy glue logic replacement, address decoding for 80C186/80C51 microcontroller systems, bus interface and arbitration logic, 5V state machines in industrial control, and education/lab platforms teaching programmable logic fundamentals. The 28-pin PLCC socket footprint remains widely supported on legacy backplanes and industrial SBCs. When designing with this part, verify that the development toolchain (MAX+PLUS II or older Altera classic support) is still available, as modern Quartus flows may not target the EP610 family. Confirm socket availability — J-lead PLCC-28 sockets are still in production but increasingly specialized. For new designs, evaluate MAX II or MAX V CPLDs as modern equivalents. This page synthesizes distributor stock and lead-time intelligence, pin-compatible same-family drop-in alternatives, and practical legacy-design notes not consolidated in the original Altera datasheet.

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EP610ILC10 - 16-Macrocell Classic EPLD, 10ns PLCC-28 | Intel
EP610ILC10

EP610ILC10 - 16-Macrocell Classic EPLD, 10ns PLCC-28 | Intel

The Intel EP610ILC10 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from Altera's EP610 family, housed in a 28-pin PLCC package with a 10ns propagation delay. It delivers pipelined data rates of up to 100 MHz and operates from a single 5V supply (4.75V to 5.25V), making it suitable for high-performance glue-logic and state-machine replacement in 5V legacy systems. A CPLD/EPLD is a non-volatile programmable logic device that retains its configuration without external memory and provides fast, deterministic propagation delays. Within the broader hierarchy, the EP610 sits as: programmable logic -> PLD -> EPLD -> Classic EPLD. It is implemented in CMOS technology, offering low static power consumption compared to bipolar PAL alternatives, and supports both UV-erasable and one-time-programmable (OTP) operation. Key features include 16 macrocells with 16 I/O lines and 4 dedicated inputs, 160 product terms, a 15ns pin-to-pin propagation delay (tPD), and a 100 MHz maximum internal clock frequency. The PAL-type AND-OR-NOT architecture with user-configurable macrocell flip-flops allows implementation of registered or combinatorial logic. The I-suffix indicates the industrial operating temperature range of -40C to +85C. The EP610ILC10 uses a classic sum-of-products architecture with a programmable AND array feeding fixed OR terms, followed by individually configurable output macrocells. Each macrocell contains a flip-flop and programmable output polarity, supporting D, T, JK, and SR flip-flop modes. The device is programmed via the Altera programming algorithm using a master programming unit, with security bit support to protect design IP. Typical applications include address decoding for microprocessor systems, bus interface glue logic, state-machine replacement, peripheral control, and 5V industrial control boards. The 100 MHz performance makes it useful in video timing and data-path control where fast, predictable logic is needed. When designing, note that the EP610 is a mature, NRND/EOL part - verify lifetime-buy status with the distributor before committing to new designs. The 28-pin PLCC package requires a through-hole or socketed footprint, so plan board layout accordingly. This page synthesizes distributor pricing, Classic EPLD family variants, and practical 5V glue-logic design notes not found in the original datasheet.

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EP610ILI-12 - 300-Gate Classic EPLD, 12ns, PLCC-28 | Altera
EP610ILI-12

EP610ILI-12 - 300-Gate Classic EPLD, 12ns, PLCC-28 | Altera

The Altera EP610ILI-12 is a 300-gate Classic EPLD from the EP610 family, packaged in a 28-pin Plastic J-Lead Chip Carrier (PLCC) and specified with a 12 ns pin-to-pin propagation delay. It provides 16 macro cells and operates from a single 5 V supply, drawing classic CMOS standby current in the I-grade industrial temperature range. Classic EPLDs (Erasable Programmable Logic Devices) are non-volatile programmable logic ICs that use EPROM/EEPROM cells to store the fuse map. They sit below modern CPLDs and FPGAs in the programmable logic hierarchy (PAL/GAL < Classic EPLD < MAX CPLD < FPGAs), and are intended for glue-logic, address decoding, state-machine and bus-arbiter functions where deterministic 12 ns timing and zero-config boot are required. Key features of the EP610ILI-12 include 300 usable gates, 16 macro cells, 4 dedicated inputs, a programmable security bit for proprietary design protection, 100% generically tested TTL-compatible I/O, and in-system 100% test coverage. The 12 ns speed grade (the "-12" suffix) places it in the mid-tier of the EP610 family, which spans from -10 to -25 speed grades. The "I" indicates the industrial temperature grade and "L" denotes low-power CMOS operation. Typical applications include TTL glue-logic replacement, address decoding for 8/16-bit microprocessors, state-machine controllers, bus arbitration, and legacy 5 V industrial control designs. Because the EP610 family is mature and now positioned as a legacy part, EP610ILI-12 is frequently specified for maintenance of existing equipment rather than new greenfield designs. When designing with this device, program it with a Classic EPLD programmer or compatible third-party tool (e.g. Altera MAX+PLUS II legacy flow). Note that Altera's PLCC package follows JEDEC MO-047 outlines and the JEDEC EEPROM cell retention spec applies for the user-programmable fuse map.

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