5CSEBA4U19C7SN vs 5CSEBA4U19I7SN Сравнение
Подробное сравнение бок о бок 5CSEBA4U19C7SN от Intel и 5CSEBA4U19I7SN от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Intel
5CSEBA4U19C7SN - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19C7SN ✓ АктивенIntel
5CSEBA4U19I7SN - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19I7SN ✓ АктивенСравнение характеристик
| Параметр | 5CSEBA4U19C7SN | 5CSEBA4U19I7SN |
|---|---|---|
| Бренд | Intel | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $218,00 | $145,00 |
| Family | Cyclone V SE SoC FPGA | — |
| Logic Elements | 40 K | 40,000 |
| Hard Processor System | Single ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz | 800 MHz |
| Process Technology | 28 nm low-power | — |
| Core Voltage (FPGA fabric) | 1.1 V | — |
| Корпус | 484-UBGA (UBGLA) 19x19 mm | 484-pin UBG A (19x19 mm) |
| Package Code | FBGA (U19) | — |
| User I/O (approx.) | 161 | — |
| I/O Standards | LVDS, LVCMOS, SSTL (1.0 V to 3.3 V) | — |
| Memory Controller | DDR3 / LPDDR2 hard controller | — |
| DSP Blocks | Variable-precision DSP blocks | — |
| Configuration Modes | JTAG, AS, PS, FPP | — |
| Bitstream Encryption | AES (256-bit) | — |
| Рабочая температура | Commercial (0C to 85C, per 'C' suffix) | -40C to +100C (Industrial) |
| Статус RoHS | Compliant | Compliant |
| Тип монтажа | Surface Mount (BGA) | Surface Mount |
| Уровень MSL | [DATA_NEEDED: MSL rating] | — |
| Series | — | Cyclone V SE SoC FPGA |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| Process Node | — | 28 nm low-power |
| Supply Voltage (Core) | — | 1.1 V (typical) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| Embedded Memory | — | [DATA_NEEDED: total Kbits of M9K blocks] |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |