5M240ZT144C5N vs 5M1270ZT144C5N Сравнение
Подробное сравнение бок о бок 5M240ZT144C5N от Intel и 5M1270ZT144C5N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ АктивенСравнение характеристик
| Параметр | 5M240ZT144C5N | 5M1270ZT144C5N |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $3,94 | $12,45 |
| Device Family | MAX V | — |
| Logic Elements (LEs) | 240 | — |
| User I/Os | 114 | 114 |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Configuration Memory | Internal Flash (non-volatile) | Flash (non-volatile, in-system programmable) |
| Maximum Operating Frequency | 1.47 GHz (internal performance) | — |
| Pin-to-Pin Logic Delay (tPD1) | 7.5 ns | — |
| Корпус | TQFP-144 (T144), 22 mm x 22 mm | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Диапазон рабочих температур | 0 C to +85 C (commercial) | — |
| Core Voltage | 1.5 V (internal LDO, derived from VCCINT) | — |
| I/O Standards Supported | LVCMOS 1.5/1.8/2.5/3.3 V, LVTTL | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | JTAG in-system programmable (Altera Quartus II) |
| Supply Voltage VCCIO | 1.5 V to 3.3 V | — |
| Тип монтажа | Surface Mount | Surface Mount |
| Статус RoHS | Compliant | Compliant |
| Уровень MSL | 3 (per JEDEC J-STD-020) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX V |
| Logic Elements | — | 1270 |
| Macrocells | — | 980 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |
| Рабочая температура | — | 0 C to +85 C (commercial grade) |