EP1C4F324C7 vs EP1C4F324C8N Сравнение
Подробное сравнение бок о бок EP1C4F324C7 от Intel и EP1C4F324C8N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP1C4F324C7 | EP1C4F324C8N |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | NRND |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $46,80 | $14,20 |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Series | Cyclone | — |
| Logic Elements | 4 000 | — |
| Logic Array Blocks / CLBs | 400 CLBs | — |
| Embedded Memory (Bits) | 78 336 | — |
| Maximum User I/O | 249 | — |
| Корпус | 324-FBGA, 19 × 19 mm, 1.0 mm pitch, lead-free | — |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Internal Frequency (max, family ref) | 405 MHz | — |
| Рабочая температура | Commercial (0 °C to +85 °C) inferred from speed grade C7 | — |
| Configuration Modes | Passive Serial (PS), Active Serial (AS), JTAG | — |
| Тип монтажа | Surface Mount (BGA) | — |
| Process Technology | CMOS, 130 nm-class (Cyclone generation) | — |
| Статус RoHS | Compliant (lead-free FBGA) | Compliant (inferred from lead-free N finish) |
| Уровень MSL | 3 (per JEDEC J-STD-020, typical for BGA-324) | — |
| Device Family | — | Cyclone |
| Programmable Logic Type | — | FPGA |
| Number of Logic Elements/Cells | — | 4000 |
| Number of LABs/CLBs | — | 400 |
| Total RAM Bits | — | 78336 |
| Number of User I/Os | — | 249 |
| Number of PLLs | — | [DATA_NEEDED: Number of PLLs] |
| Maximum Internal Frequency (datasheet listing) | — | 405 MHz |
| Корпус / Типоразмер | — | 324-ball FBGA (19 mm x 19 mm, 1.0 mm pitch) |
| Number of Terminals | — | 324 |
| Способ монтажа | — | Surface Mount |
| Диапазон рабочих температур | — | 0°C to +85°C (commercial grade) |
| Speed Grade | — | C8 (speed grade 8) |
| Solder Finish | — | Lead-free (N suffix) |
| Configuration | — | SRAM-based, external configuration |