EP20K1000CF672C7GZ vs EP20K1000CF33C9ES Сравнение
Подробное сравнение бок о бок EP20K1000CF672C7GZ от Intel и EP20K1000CF33C9ES от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA
EP20K1000CF33C9ES ⚠ Последняя закупкаСравнение характеристик
| Параметр | EP20K1000CF672C7GZ | EP20K1000CF33C9ES |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Последняя закупка |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $162,40 | $215,00 |
| Family | APEX 20KC | APEX-20KC |
| Series | APEX-20KC® | — |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| System Gates | 1,000,000 | — |
| Logic Elements / Cells | 38,400 | — |
| Total RAM Bits | 327,680 | — |
| Number of I/O | 508 | — |
| Number of LABs/CLBs | 2560 | — |
| Number of EABs | 160 | — |
| Number of Logic Elements per EAB | 2048 bits | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Корпус / Типоразмер | 672-FBGA (672-BBGA) | — |
| Supplier Device Package | 672-FBGA (27x27 mm, 1.27 mm pitch) | — |
| Тип монтажа | Surface Mount | — |
| Speed Grade | C7 (7 ns pin-to-pin delay, commercial) | C9 |
| Рабочая температура | 0°C to +85°C | 0 C to +85 C (commercial) |
| Статус RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | Yes | — |
| Process Technology | 0.15 µm CMOS | 0.18 um CMOS |
| Typical Gate Count | — | 1,000,000 system gates |
| Logic Elements | — | 38,400 |
| Logic Array Blocks (LABs) | — | 3,840 |
| Embedded System Blocks (ESBs) | — | 212 |
| Total Embedded RAM Bits | — | 327,680 bits |
| Maximum User I/O Pins | — | 708 |
| Корпус | — | 1,020-ball FineLine BGA (FBGA) |
| Logic Element Architecture | — | 4-input LUT with dedicated carry chain |
| Maximum Embedded RAM per ESB | — | 32,768 bits (dual-port, FIFO support) |
| Phase-Locked Loops | — | Up to 4 enhanced PLLs |
| MultiVolt I/O Support | — | 1.8V / 2.5V / 3.3V / 5.0V |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Method | — | Passive serial / Passive parallel / JTAG |
| Lead-Free | — | [DATA_NEEDED: lead-free finish status] |