EP20K400CF672C7ES vs EP20K400CF672C7N Сравнение
Подробное сравнение бок о бок EP20K400CF672C7ES от Altera и EP20K400CF672C7N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP20K400CF672C7ES | EP20K400CF672C7N |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $152,00 | $160,00 |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | — |
| Device Type | Loadable PLD / FPGA | — |
| Logic Elements (Cells) | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (Bits) | 212,992 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 488 | 488 |
| I/O Lines | 484 | — |
| Input Lines | 488 | — |
| Number of PLLs | 4 | — |
| Maximum Internal Clock Frequency | 375.94 MHz | — |
| Propagation Delay | 1.4 ns | 2.5 ns (catalog) / 1.48 ns (some catalog) |
| Process Technology | 0.18 um CMOS | 0.18-micron CMOS, all-layer copper interconnect |
| Core Voltage | 1.8 V | — |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | C7 (commercial, -7) | — |
| Рабочая температура | 0C to +85C (commercial) | 0 C to 85 C (Commercial) |
| Package Type | 672-ball FineLine BGA | — |
| Package Code | FC-FBGA-B672 | — |
| Ball Pitch | 1.000 mm | — |
| Тип монтажа | Surface Mount | Surface Mount (BGA) |
| Статус RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status not in provided data] |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Embedded Memory | — | 488 Kbits |
| User I/O (per catalog) | — | 480 / 502 (per source) |
| Корпус | — | 672-ball FineLine BGA (FC-FBGA / BBGA) |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 3.3 V / 2.5 V banked |
| Maximum Frequency | — | 375.94 MHz (internal) |
| Уровень MSL | — | 3 (per JEDEC J-STD-020) |
| Configuration Modes | — | PS, PPS, JTAG |