EP20K400FI672-3V vs EP20K400FC672-3V Сравнение
Подробное сравнение бок о бок EP20K400FI672-3V от Intel и EP20K400FC672-3V от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP20K400FI672-3V | EP20K400FC672-3V |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $285,00 | $152,00 |
| Family | APEX 20K (EP20K400) | APEX 20KC |
| Logic Elements | 16,640 | — |
| Maximum Gates | 400,000 | — |
| Typical Gates | [DATA_NEEDED: typical gates value] | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Total User I/O + Dedicated Inputs | 496 + 6 (variant dependent) | — |
| Максимальная тактовая частота | 714.2 MHz | — |
| Speed Grade | -3 (faster) | -3 |
| Core Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | 0.18 µm CMOS, 4 metal layers | 0.22 µm |
| Корпус | 672-ball FineLine BGA (BBGA), 1.0 mm pitch | — |
| Тип монтажа | Surface Mount | Surface Mount |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| Supported I/O Standards | LVCMOS, LVTTL, SSTL, GTL+, HSTL | — |
| Configuration Modes | JTAG, passive serial, passive parallel | — |
| Статус RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Рабочая температура | -40 °C to +85 °C (industrial) | [DATA_NEEDED: operating temperature range] |
| Уровень MSL | [DATA_NEEDED: MSL rating] | — |
| Series | — | APEX-20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements / Cells | — | 16640 |
| System Gates | — | 400000 |
| Total RAM Bits | — | 212992 |
| Number of I/O | — | 502 |
| Number of LABs/CLBs | — | 1664 |
| Number of Logic Elements | — | 16640 |
| Supply Voltage (Core) | — | 1.71 V to 1.89 V |
| Корпус / Типоразмер | — | 672-BBGA, FCBGA |
| Supplier Device Package | — | 672-FBGA (27x27) |
| Maximum Internal Frequency | — | 167 MHz (typical) |
| Pin-to-Pin Delay | — | 3.6 ns |
| Programmability Type | — | In-system (JTAG IEEE 1149.1) |