EPC16JC88 vs EPC16UC88 Сравнение
Подробное сравнение бок о бок EPC16JC88 от Altera и EPC16UC88 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC16JC88 | EPC16UC88 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | Memory ICs | Memory ICs |
| Статус жизненного цикла | NRND | Unknown |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $17,95 | $0,00 |
| Manufacturer | Altera (now Intel FPGA) | — |
| Family | Enhanced Configuration Device (EPC4 / EPC8 / EPC16) | — |
| Device Function | In-system programmable configuration PROM for SRAM-based FPGAs | — |
| Density | 16 Mbit | — |
| Programmability | In-system programmable via IEEE 1149.1 JTAG | — |
| Configuration Interface | Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | — |
| Корпус | 88-ball UBGA (11 x 8 mm), JEDEC designation C88 | 88-UBGA (11x8) |
| Operating Temperature Grade | Industrial (J suffix) | — |
| Напряжение питания | [DATA_NEEDED: VCC operating range] | 3.3 V core and I/O |
| Supported FPGA Families | Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface) | — |
| Configuration Clock | Driven by target FPGA during configuration | — |
| Programming Interface | JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO | — |
| Multi-Device Configuration | Supports daisy-chain configuration of multiple FPGAs | — |
| Уровень чувствительности к влаге (MSL) | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] | — |
| Статус RoHS | [DATA_NEEDED: RoHS compliance declaration] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Без галогенов | [DATA_NEEDED: halogen-free status] | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Тип монтажа | — | Surface mount |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Рабочая температура | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |