EPC16UC88AB vs EPC16JC88 Сравнение
Подробное сравнение бок о бок EPC16UC88AB от Altera и EPC16JC88 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC16UC88AB | EPC16JC88 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | Memory ICs | Memory ICs |
| Статус жизненного цикла | Активен | NRND |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $17,40 | $17,95 |
| Тип памяти | Non-volatile Flash Configuration PROM | — |
| Размер памяти | 16 Mbit | — |
| Configuration Interface | Passive Serial (PS), Active Serial (AS), JTAG (IEEE 1149.1) | Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) |
| In-System Programmable | Yes (via JTAG) | — |
| Multi-Boot Support | Yes | — |
| Remote System Upgrade | Yes | — |
| Page Mode | Yes (fast parallel configuration) | — |
| Operating Voltage | 3.3 V | — |
| Корпус | 88-LFBGA (FineLine BGA) | 88-ball UBGA (11 x 8 mm), JEDEC designation C88 |
| Package Code | UC88 | — |
| Compatible FPGA Families | Altera Stratix, Cyclone, Arria series | — |
| Диапазон рабочих температур | [DATA_NEEDED: operating temperature range] | — |
| Уровень MSL | [DATA_NEEDED: MSL level] | — |
| Статус RoHS | Compliant (lead-free) | [DATA_NEEDED: RoHS compliance declaration] |
| Тип монтажа | Surface Mount | — |
| Datasheet Document | EPC4, EPC8 & EPC16 Enhanced Configuration Devices Data Sheet | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Family | — | Enhanced Configuration Device (EPC4 / EPC8 / EPC16) |
| Device Function | — | In-system programmable configuration PROM for SRAM-based FPGAs |
| Density | — | 16 Mbit |
| Programmability | — | In-system programmable via IEEE 1149.1 JTAG |
| Operating Temperature Grade | — | Industrial (J suffix) |
| Напряжение питания | — | [DATA_NEEDED: VCC operating range] |
| Supported FPGA Families | — | Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface) |
| Configuration Clock | — | Driven by target FPGA during configuration |
| Programming Interface | — | JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO |
| Multi-Device Configuration | — | Supports daisy-chain configuration of multiple FPGAs |
| Уровень чувствительности к влаге (MSL) | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |
| Без галогенов | — | [DATA_NEEDED: halogen-free status] |