EPC1LC20AL3894 vs EPC1LC20-WCEC52 Сравнение
Подробное сравнение бок о бок EPC1LC20AL3894 от Intel и EPC1LC20-WCEC52 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC1LC20AL3894 | EPC1LC20-WCEC52 |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | Memory ICs | Memory ICs |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $5,45 | $7,45 |
| Тип памяти | OTP Configuration PROM (EPROM-based) | OTP Configuration PROM (Anti-fuse) |
| Memory Capacity | 1 Mbit (212,942 × 1-bit) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V nominal) | 3.3 V |
| Configuration Clock Frequency | Up to 8 MHz | — |
| Configuration Interface | Serial (Altera standard 4-wire: DATA, DCLK, nCS, nINIT_CONF) | — |
| Корпус | 20-pin PLCC (J-lead) | 20-pin PLCC (J-lead, through-hole, 9x9 mm) |
| Package Dimensions | 9.0 × 9.0 × 4.5 mm (PLCC-20) | — |
| Рабочая температура | -40 °C to +85 °C (industrial) | -40C to +85C (industrial) |
| Programming Method | Factory / Altera programming service (one-time only) | — |
| Erasure | Windowed package supports UV erase (ceramic DIP variant); PLCC is OTP | — |
| Выходная конфигурация | Serial data out on DCLK rising edge | — |
| Compatible FPGA Families | APEX, ACEX, FLEX 10K, MAX 7000S/AE/B, Cyclone (legacy) | Cyclone, Stratix, APEX, ACEX, MAX series |
| Тип монтажа | Surface Mount / Socket (PLCC socket compatible) | — |
| Статус RoHS | Unknown — verify with manufacturer | [DATA_NEEDED: RoHS status] |
| Статус жизненного цикла | Obsolete (EOL announced by Altera / Intel PSG) | Obsolete (recommended replacement: EPCQ family or newer serial config devices) |
| Shipping Variant Suffix | AL3894 (tape-and-reel / specific Altera part marking) | — |
| Размер памяти | — | 1 Mbit (1,048,576 bits) |
| Организация памяти | — | 212,942 x 1 bit |
| Интерфейс | — | Serial (Altera FPP/PS configuration protocol) |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| I/O Voltage Tolerance | — | 5.0 V (FPGA interface) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Programmability | — | One-Time Programmable (OTP) |
| Package Mounting | — | Through-hole (also accepts PLCC socket) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Programming Interface | — | JTAG (IEEE Std 1149.1) ISP |
| Число выводов | — | 20 |