EPC2T132N vs EPC2LS20U Сравнение
Подробное сравнение бок о бок EPC2T132N от Altera и EPC2LS20U от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC2T132N | EPC2LS20U |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | Memory ICs |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $17,80 | $4,25 |
| Тип памяти | Flash (NOR, serial configuration) | — |
| Memory Capacity | 1.6 Mbit (2 Mbit raw, 1.6 Mbit usable) | — |
| Serial Clock Frequency | 10 MHz maximum | — |
| Интерфейс | Altera serial configuration (4-wire JTAG for ISP) | Altera serial configuration / JTAG |
| Напряжение питания | 3.0 V to 3.6 V | — |
| Рабочая температура | -40C to +85C (industrial) | [DATA_NEEDED: Operating Temperature] |
| Корпус | TQFP-32 (T132) | 20-PLCC (J-lead, 9x9 mm) |
| Тип монтажа | Surface Mount | — |
| Program/Erase Endurance | 100,000 cycles per sector | — |
| Data Retention | 20 years minimum | — |
| In-System Programmable | Yes (IEEE 1149.1 JTAG) | — |
| Configuration Compatibility | APEX II, APEX 20K, ACEX 1K, FLEX 10K/10KE/6000, Cyclone, Stratix, Mercury | — |
| Multi-Device Daisy Chain | Yes (supported) | — |
| Статус RoHS | [DATA_NEEDED: RoHS status] | — |
| Уровень MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL Level] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | In-System Programmable Configuration PROM |
| Memory Density | — | 1.6 Mbit |
| Operating Voltage (VCC) | — | 3.3 V |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead-Free / RoHS | — | Yes (per "U" suffix) |
| Supported FPGA Families | — | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 |
| Configuration Modes | — | PS (Passive Serial), AS, FPP |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Done Pin | — | Yes (open-drain programmable polarity) |
| nSTATUS Pin | — | Yes (open-drain error flag) |
| nCONFIG Pin | — | Yes (reset/reconfiguration input) |
| DCLK Output | — | Yes (configuration clock to FPGA) |
| Compliance | — | RoHS (Pb-free per U suffix) |