EPC8QC100-T vs EPC8QC100DM Сравнение
Подробное сравнение бок о бок EPC8QC100-T от Altera и EPC8QC100DM от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC8QC100-T | EPC8QC100DM |
|---|---|---|
| Бренд | Altera | Intel |
| Категория | Memory ICs | EEPROM |
| Статус жизненного цикла | NRND | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $9,85 | $17,10 |
| Тип памяти | Enhanced Configuration PROM (Flash) | Non-volatile configuration PROM |
| Размер памяти | 8 Mbit | 8 Mb (1 MB) |
| Configuration Schemes | Passive Serial (PS), Concurrent, Parallel | — |
| FPGA Compatibility | Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K | — |
| In-System Programmability | Yes (IEEE 1532 / JTAG) | — |
| Data Compression | Yes (built-in) | — |
| Корпус | PQFP-100 (20 x 14 mm) | 100-PQFP (20 x 14 mm) |
| Тип монтажа | Surface Mount | Surface Mount |
| Shipping Packaging | Tape & Reel (suffix -T) | — |
| Рабочая температура | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial / DM suffix) |
| Напряжение питания | [DATA_NEEDED: core and I/O supply voltage] | — |
| Статус RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Max Configuration Clock | [DATA_NEEDED: DCLK maximum frequency] | — |
| Manufacturer | Altera (now Intel FPGA) | — |
| Интерфейс | — | Serial (Passive Serial / Passive Parallel Synchronous / Active Serial) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Maximum DCLK Frequency | — | 40 MHz |
| In-System Programming | — | Yes (IEEE 1149.1 / IEEE 1532 JTAG) |
| Cascade Support | — | Yes - two EPC8 devices for 16 Mb |
| Уровень MSL | — | 1 (Unlimited) |
| Lead-Free / Halogen-Free | — | Lead-free (per supplier); halogen status not in datasheet excerpt |
| Compatible FPGA Families | — | Cyclone, Cyclone II, Cyclone III, Stratix, Arria |
| Configuration Modes | — | PS, PPS, AS (with appropriate FPGA master) |
| Programming Cycles | — | [DATA_NEEDED: minimum erase/write endurance cycles] |