EPC8QC100C vs EPC8QC100DM Сравнение
Подробное сравнение бок о бок EPC8QC100C от Altera и EPC8QC100DM от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC8QC100C | EPC8QC100DM |
|---|---|---|
| Бренд | Altera | Intel |
| Категория | Memory ICs | EEPROM |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $9,95 | $17,10 |
| Тип памяти | Flash-based Configuration PROM | Non-volatile configuration PROM |
| Размер памяти | 8 Mbit | 8 Mb (1 MB) |
| Configuration Schemes | Passive Serial, Concurrent (up to 8 chains), Parallel | — |
| Target FPGA Compatibility | Altera APEX, Stratix, Cyclone, ACEX, Mercury, FLEX series | — |
| Корпус | 100-Pin PQFP (20x14 mm) | 100-PQFP (20 x 14 mm) |
| Тип монтажа | Surface Mount | Surface Mount |
| Operating Voltage | 3.3 V typical | — |
| Рабочая температура | -40C to +85C (industrial) | -40 C to +85 C (industrial / DM suffix) |
| Programming Interface | JTAG / Altera ByteBlaster / USB-Blaster | — |
| Configuration Interface | Serial (DCLK/DATA) or Parallel | — |
| Max Configuration Clock | [DATA_NEEDED: max DCLK frequency] | — |
| Flash Erase/Program Cycles | [DATA_NEEDED: endurance cycles] | — |
| Статус RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Уровень MSL | [DATA_NEEDED: MSL rating] | 1 (Unlimited) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Интерфейс | — | Serial (Passive Serial / Passive Parallel Synchronous / Active Serial) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Maximum DCLK Frequency | — | 40 MHz |
| In-System Programming | — | Yes (IEEE 1149.1 / IEEE 1532 JTAG) |
| Cascade Support | — | Yes - two EPC8 devices for 16 Mb |
| Lead-Free / Halogen-Free | — | Lead-free (per supplier); halogen status not in datasheet excerpt |
| Compatible FPGA Families | — | Cyclone, Cyclone II, Cyclone III, Stratix, Arria |
| Configuration Modes | — | PS, PPS, AS (with appropriate FPGA master) |
| Programming Cycles | — | [DATA_NEEDED: minimum erase/write endurance cycles] |