EPF8452ALI84-4 vs EPF8636ALC84-4 Сравнение
Подробное сравнение бок о бок EPF8452ALI84-4 от Altera и EPF8636ALC84-4 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPF8452ALI84-4 | EPF8636ALC84-4 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | NRND | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $9,75 | $24,30 |
| Family | FLEX 8000 | FLEX 8000 |
| Logic Elements | 336 | — |
| Usable Gates | 4,000 | — |
| User I/Os | 68 | — |
| Operating Frequency (max) | 125 MHz | — |
| Process Technology | 0.42 µm CMOS | 0.42 µm CMOS SRAM |
| Supply Voltage (VCC) | 5 V | — |
| I/O Voltage (MultiVolt) | 3.3 V or 5.0 V | — |
| Package Type | 84-pin PLCC (J-Lead) | — |
| Число выводов | 84 | — |
| Speed Grade | -4 | -4 |
| Рабочая температура | 0 °C to 70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Configuration Method | SRAM, requires external configuration memory | Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| Configuration Devices Supported | EPC1, EPC1064, EPC1213, EPC1441, parallel EPROM | — |
| Programming | In-circuit reconfigurable (ICR) via JTAG or controller | — |
| Тип монтажа | Surface Mount (PLCC socket compatible) | Surface Mount / Socket |
| Статус RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (legacy PLCC, lead-bearing) |
| Уровень MSL | [DATA_NEEDED: MSL level] | — |
| Number of Logic Cells | — | 504 |
| Number of Logic Array Blocks (LABs) | — | 63 |
| Maximum Usable Gates | — | 6,000 |
| Number of User I/O Pins | — | 68 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage (84-pin PLCC) | — | 5.0 V only (3.3 V I/O NOT supported on this package) |
| Operating Current (typical) | — | 10 mA |
| Корпус | — | 84-Pin PLCC (J-Lead) |
| Configuration Memory Type | — | Volatile SRAM (requires boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |