EPM3128ATI144-10 vs EPM3128ATC144-7N Сравнение
Подробное сравнение бок о бок EPM3128ATI144-10 от Altera и EPM3128ATC144-7N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM3128ATI144-10 - MAX 3000A CPLD 128 Macro 98 I/O TQFP-144 | Intel/Altera
EPM3128ATI144-10 Nrnd
Сравнение характеристик
| Параметр | EPM3128ATI144-10 | EPM3128ATC144-7N |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | NRND | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $10,85 | $9,25 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 2,500 | — |
| Macro Cells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 98 | 96 |
| Число выводов | 144 | 144 |
| Корпус | TQFP-144 (FINE LINE) | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Counter Frequency | 98 MHz typical | Up to 227.3 MHz |
| Logic Family | CMOS, EEPROM-based | CMOS |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) | Compatible with PCI Local Bus Specification Rev. 2.2 |
| Рабочая температура | -40C to +85C (Industrial) | 0 °C to +70 °C (commercial) |
| Тип монтажа | Surface Mount (Gull-Wing TQFP) | Surface Mount (SMD/SMT) |
| Статус RoHS | Compliant (lead-free TQFP) | Lead-free (-7N suffix indicates Pb-free finish) |
| Series | — | MAX 3000A |
| Architecture | — | EEPROM-based, MAX architecture |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | Up to 10,000 |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | — | Yes, via JTAG (IEEE 1149.1) |