EPM3256ATI144-7N vs EPM3256ATC144-10N Сравнение
Подробное сравнение бок о бок EPM3256ATI144-7N от Altera и EPM3256ATC144-10N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteAltera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Последняя закупкаСравнение характеристик
| Параметр | EPM3256ATI144-7N | EPM3256ATC144-10N |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Последняя закупка |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $10,95 | $14,50 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | 5,000 (up to 10,000 usable in family) |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 116 | — |
| Propagation Delay (tPD) | 7.5 ns (typical) | 10 ns |
| Maximum Internal Frequency | 126.6 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| MultiVolt I/O Logic Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG / ISP | IEEE Std. 1532 compliant | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| Hot-Socketing Support | Yes | — |
| Корпус | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-LQFP (TQFP, ATC suffix) |
| Рабочая температура | -40C to +85C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Статус RoHS | Compliant (lead-free) | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Series | — | MAX 3000A |
| Macro Cells | — | 256 |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| Тип монтажа | — | Surface Mount |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |