EPM5128GC vs EPM5032DC-2 Сравнение
Подробное сравнение бок о бок EPM5128GC от Altera и EPM5032DC-2 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPM5128GC | EPM5032DC-2 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $19,20 | $8,75 |
| Family | MAX 5000 | — |
| Macrocells | 128 | 32 |
| Usable Gates | 2,500 | — |
| Logic Elements / LABs | [DATA_NEEDED: LAB count] | — |
| User I/Os | 68 | — |
| Package Type | WPGA (Windowed Ceramic Pin Grid Array) | — |
| Package Code | WPGA | — |
| Number of Terminals | 68 | — |
| Terminal Form | PIN/PEG (through-hole PGA with alignment pegs) | — |
| Package Shape | Square | — |
| Temperature Grade | Commercial | — |
| Supply Voltage (Vcc) | 5 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | EPLD, programmable AND/OR array with fixed OR plane | — |
| Propagation Delay (tpd) | [DATA_NEEDED: tpd in ns] | — |
| Maximum Frequency (fmax) | [DATA_NEEDED: fmax in MHz] | — |
| Programmable Security Bit | Yes | — |
| Configuration Memory | Non-volatile UV-EPROM (windowed ceramic) | EPROM (one-time programmable per generation; UV-erasable variants exist) |
| Тип монтажа | Through-Hole (PGA socket required) | Through-Hole (DIP) |
| Статус RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX 5000 |
| Usable Gates (typical) | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| Корпус | — | 20-pin CDIP (Ceramic DIP) |
| Speed Grade | — | -2 (tPD ~25 ns, commercial) |
| Supply Voltage (VCC) | — | 5 V (single supply, +/-5%) |
| Рабочая температура | — | 0C to +70C (commercial grade) |
| Programmable Pins / I/O | — | 20 pins (JEDEC-standard 0.300" ceramic DIP) |
| Programming Interface | — | Altera ByteBlaster / parallel-port JTAG-style ISP |
| Interconnect | — | Programmable Interconnect Array (PIA) with deterministic timing |
| Уровень MSL | — | Not applicable (through-hole hermetic ceramic) |