EPM9560RC-15 vs EPM9560R1208-20 Сравнение
Подробное сравнение бок о бок EPM9560RC-15 от Altera и EPM9560R1208-20 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 ⚠ Последняя закупкаСравнение характеристик
| Параметр | EPM9560RC-15 | EPM9560R1208-20 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Последняя закупка | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $30,10 | $22,40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 6,000 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | — |
| Maximum User I/O Pins | 191 | — |
| Pin-to-Pin Delay (tPD1) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Рабочая температура | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Корпус | 240-pin RQFP (32x32 mm) | R-1208 (BGA-style fine-pitch) |
| Тип монтажа | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM, third-generation MAX architecture |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Статус RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | Yes (IEEE 1149.1 JTAG) |
| Logic Array Blocks | — | 52 (typical for 560 macrocells) |
| Maximum User I/O | — | 212 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS EEPROM |
| Boundary-Scan Test | — | JTAG IEEE Std. 1149.1 |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |