EPM9560RC208-3 vs EPM9560RC208-15 Сравнение
Подробное сравнение бок о бок EPM9560RC208-3 от Altera и EPM9560RC208-15 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera
EPM9560RC208-3 ⚠ Последняя закупкаСравнение характеристик
| Параметр | EPM9560RC208-3 | EPM9560RC208-15 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Последняя закупка | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $58,50 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Maximum Operating Frequency | [DATA_NEEDED: f_MAX] | — |
| Pin-to-Pin Delay (speed grade -3) | approximately 3 ns (slowest grade) | — |
| Speed Grade | -3 | -15 (15 ns pin-to-pin) |
| Корпус | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| I/O Voltage Tolerance | 5V | — |
| Process Technology | 0.5 µm CMOS EPROM | — |
| Programming Interface | ByteBlaster / BitBlaster (JTAG-compatible) | — |
| Рабочая температура | [DATA_NEEDED: industrial / commercial range] | [DATA_NEEDED: operating temperature range] |
| Статус RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Lifecycle | Mature / Last-time-buy (per Altera PDN for selected MAX 9000 ordering codes) | — |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Напряжение питания | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Тип монтажа | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |