MK2703SLF vs MK2703SI Сравнение
Подробное сравнение бок о бок MK2703SLF от Renesas Electronics и MK2703SI от Renesas Electronics. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | MK2703SLF | MK2703SI |
|---|---|---|
| Бренд | Renesas Electronics | Renesas Electronics |
| Категория | Clock & Timing | Clock & Timing |
| Статус жизненного цикла | Unknown | Unknown |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $0,00 | $0,00 |
| Device Type | PLL audio clock synthesizer | PLL audio clock synthesizer |
| Reference Input Frequency | 27 MHz crystal or clock input | — |
| Количество выходов | Buffered reference clock and selectable audio clock | — |
| PLL Technology | Analog phase-locked loop technology | — |
| Input Clock Count | 1 | — |
| Корпус | 8-SOIC | 8-SOIC (0.154 inch, 3.90 mm width) |
| Package Width | 0.154 in / 3.90 mm | — |
| Тип монтажа | Surface mount | Surface mount |
| Application Category | Set-top box and multimedia clock generation | — |
| Рабочее напряжение питания | [DATA_NEEDED: operating supply voltage] | — |
| Output Frequency Options | [DATA_NEEDED: output frequency options] | — |
| Output Jitter | [DATA_NEEDED: output jitter] | — |
| Phase Noise | [DATA_NEEDED: phase noise] | — |
| Crystal Load Capability | [DATA_NEEDED: crystal load capacitance] | — |
| Output Drive Capability | [DATA_NEEDED: output drive capability] | — |
| Диапазон рабочих температур | [DATA_NEEDED: operating temperature range] | — |
| Power Consumption | [DATA_NEEDED: power consumption] | — |
| Статус RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| Automotive Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Target Application | — | Set-top box and multimedia systems |
| Architecture | — | Phase-locked-loop clock synthesis |
| Jitter Classification | — | Low-jitter |
| Cost Positioning | — | Low-cost |
| Input Frequency Range | — | [DATA_NEEDED: input frequency range] |
| Output Frequency Range | — | [DATA_NEEDED: output frequency range] |
| Напряжение питания | — | [DATA_NEEDED: supply voltage] |
| Output Clock Count | — | [DATA_NEEDED: number and type of clock outputs] |
| Reference Input | — | [DATA_NEEDED: reference input requirement] |
| PLL Loop Filter | — | [DATA_NEEDED: PLL loop-filter requirements] |
| Рабочая температура | — | [DATA_NEEDED: operating temperature range] |
| Absolute Maximum Supply Voltage | — | [DATA_NEEDED: absolute maximum supply voltage] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |
| Число выводов | — | 8 pins |
| Manufacturer Document | — | MK2703 Datasheet |