MPC563MZP56 vs MPC561CZP40 Сравнение
Подробное сравнение бок о бок MPC563MZP56 от NXP Semiconductors и MPC561CZP40 от NXP Semiconductors. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
NXP Semiconductors
MPC561CZP40 - 40MHz PowerPC Qorivva MCU, 388-PBGA | NXP
MPC561CZP40 ⚠ Последняя закупкаСравнение характеристик
| Параметр | MPC563MZP56 | MPC561CZP40 |
|---|---|---|
| Бренд | NXP Semiconductors | NXP Semiconductors |
| Категория | Microcontrollers | Microcontrollers |
| Статус жизненного цикла | NRND | Последняя закупка |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $17,95 | $51,75 |
| Core Architecture | PowerPC MPC5xx (32-bit) | PowerPC (MPC5xx / Qorivva family) |
| Maximum CPU Frequency | 56 MHz | — |
| Program Memory (Flash) | 512 KB (512K x 8) | — |
| RAM Size | 36 KB | — |
| Operating Voltage | 5 V (typical) | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Корпус | 388-PBGA (27 x 27 mm) | — |
| Тип монтажа | Surface Mount (BGA) | Surface Mount (BGA) |
| Temperature Grade | Standard (P) | — |
| Рабочая температура | [DATA_NEEDED: operating temperature range] | — |
| Peripherals | Peripheral pin multiplexing, CAN, SPI, serial interfaces | — |
| Code Compression | Yes (on-chip) | — |
| Intermodule Bus | Common IMB | — |
| Debug Interface | Background Debug Mode (BDM) | — |
| Уровень MSL | [DATA_NEEDED: MSL rating] | MSL3 (typical for large PBGA) |
| Статус RoHS | Compliant (per distributor listing) | — |
| Manufacturer | NXP USA Inc. (formerly Freescale/Motorola) | — |
| Core Count | — | Single-core |
| Разрядность шины данных | — | 32-bit |
| Максимальная тактовая частота | — | 40 MHz |
| Program Memory Type | — | ROMless (no internal Flash) |
| Package Type | — | 388-PBGA (Plastic Ball Grid Array) |
| Package Dimensions | — | 27 x 27 mm |
| Диапазон рабочих температур | — | -40C to +85C |
| Automotive Grade | — | AEC-Q100 Grade compliant (Automotive) |
| Supply Voltage Range | — | [DATA_NEEDED: Vcore/Vio supply range] |
| On-chip SRAM Size | — | [DATA_NEEDED: SRAM bytes] |
| External Bus Interface | — | Yes (32-bit bus, chip-selects via SIU) |
| ADC Channels | — | QADC (Queued ADC) - multi-channel |
| Timer Processing Unit | — | TPU - integrated motion-control timer |
| Peripheral Pin Multiplexing | — | Yes (SIU-controlled routing) |
| Lead-free / RoHS | — | Lead-free finish; RoHS compliance varies by date code |