RTAX250SL-CG624V vs RTAX250SL-1CG624E Сравнение

Подробное сравнение бок о бок RTAX250SL-CG624V от Microchip Technology и RTAX250SL-1CG624E от Microchip Technology. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.

Microchip Technology
RTAX250SL-CG624V RTAX250SL-CG624V - 250k-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-CG624V - 250k-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-CG624V ✓ Активен
Microchip Technology
RTAX250SL-1CG624E RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip

RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip

RTAX250SL-1CG624E ✓ Активен

Сравнение характеристик

Параметр RTAX250SL-CG624V RTAX250SL-1CG624E
Бренд Microchip Technology Microchip Technology
Категория FPGA & CPLD FPGA & CPLD
Статус жизненного цикла Активен Активен
Наличие In Stock In Stock
Цена за единицу (USD) $10.000,00 $1,00
Equivalent System Gates 250000 250,000 gates
Logic Cells 4224 4224
CLB Count 2816 —
User I/O (Inputs) 248 —
User I/O (Outputs) 248 —
Core Supply Voltage 1.425 V to 1.575 V 1.5 V (1.425 V to 1.575 V)
Process Technology CMOS 0.15 um CMOS
Program Technology Antifuse (one-time programmable) —
Корпус 624-pin Ceramic Column Grid Array (CG624) 624-ball Ceramic Column Grid Array (CCGA-624)
Embedded SRAM Yes (with built-in FIFO control logic) —
Configuration Device Required No (live at power-up) —
Radiation Tolerance Radiation-tolerant (space flight qualified family) SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day
Family RTAX-S/SL and RTAX-DSP RadTolerant FPGAs —
Рабочая температура [DATA_NEEDED: operating temperature range] -55C to +125C
Speed Grade Standard (C) commercial flight grade; -1 speed variant available —
Тип монтажа Surface Mount Surface Mount (ceramic column grid array)
Статус RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Configurable Logic Blocks (CLBs) — 2816
User I/O — 248 inputs / 248 outputs
Maximum Combinatorial Delay (CLB) — 0.93 ns
Maximum System Frequency — 649 MHz
Logic Family — CMOS
SEU Mitigation — SEU-hardened registers (no external TMR required)
Embedded Memory — Embedded SRAM with built-in FIFO control logic
Configuration — Live-at-power-up, true single-chip operation
I/O Supply Voltage — [DATA_NEEDED: I/O bank voltage]

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