ADS6122IRHBR - 12-bit 65MSPS ADC with DDR LVDS/CMOS Outputs | Texas Instruments
Артикул: ADS6122IRHBR ✓ Активен| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $17.1 | $171,00 |
| 100 | $15.4 | $1.540,00 |
| 500 | $13.95 | $6.975,00 |
| 1.000 | $12.5 | $12.500,00 |
ADS6122IRHBR Обзор
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltage signals and converts them into discrete digital codes for processing by FPGAs, ASICs, DSPs, or microcontrollers. The ADS6122IRHBR uses a pipelined architecture, a popular topology for high-speed, moderate-resolution converters because it balances sample rate, latency, and power consumption. It sits in the broader taxonomy of data converters -> ADC -> pipelined ADC -> high-speed low-power ADC -> power management and signal chain IC.
Key features of the ADS6122IRHBR include 12-bit resolution at up to 65 MSPS, selectable CMOS or DDR LVDS digital interface, low power consumption suitable for portable and densely-populated boards, an internal sample-and-hold, and a 3.3 V analog supply. The pipelined core delivers low latency and excellent spurious-free dynamic range (SFDR) for communications, imaging, and instrumentation front ends. Internal reference and high-impedance analog inputs simplify external BOM.
Architecturally, the ADS6122IRHBR combines a high-bandwidth differential input sample-and-hold, a multi-stage switched-capacitor pipeline, and an output stage that can be configured for either single-data-rate CMOS or double-data-rate LVDS. The DDR LVDS mode is particularly valuable for interfacing with high-speed FPGAs and ASICs where board trace count must be minimized at high sampling rates.
Typical applications include wireless communication baseband IF sampling, medical imaging front ends, handheld oscilloscopes, radar signal processing, and industrial test and measurement equipment. The 65 MSPS sample rate is well-suited for IF digitization in narrow-band receivers and for ultrasound beamforming preprocessing.
When designing with this device, place input RC anti-aliasing networks close to the analog input pins, provide a clean low-noise 3.3V analog rail separate from the digital 3.3V domain, and tie the LVDS/CMOS mode select pin correctly during PCB layout to avoid mode contention. Decouple the supply pins with 0.1 uF and 10 uF capacitors.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes that go beyond the information found in the manufacturer datasheet.
Аналоги без доработки для ADS6122IRHBR — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с ADS6122IRHBR (тот же форм-фактор и посадочное место) — отличается по RoHS Status, Package, Analog Supply Voltage, Operating Temperature Range, Output Interface.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
ADS6123IRHBR
✅ Прямая замена✓ В наличии
$9.4 / шт.
Открыть даташит →ADS6124IRHBR
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADS6125IRHBR
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADS6122IRHBT
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADS6122IRHB25
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADS6122IRHBR Максимальные параметры и электрические характеристики
| Разрешение | 12 bits |
| Sample Rate (max) | 65 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Type | Differential |
| Digital Output Interface | Selectable CMOS or DDR LVDS (parallel) |
| Analog Supply Voltage | 3.3 V |
| Диапазон рабочих температур | -40 C to +85 C |
| Корпус | VQFN-32 (RHB) 5x5 mm |
| Тип монтажа | Surface Mount |
| Статус RoHS | Compliant (per distributor listings) |
| Lead-Free | Yes |
| Family / Series | ADS612x (ADS6122/23/24/25) |
| Family Pin Compatibility | Yes - ADS6122/23/24/25 share the same 32-pin VQFN footprint |
Конфигурация выводов ADS6122IRHBR
| Контакт 1 | AVDD — Analog 3.3V supply |
| Контакт 2 | INP — Differential analog input positive |
| Контакт 3 | INN — Differential analog input negative |
| Контакт 4 | VCM — Common-mode voltage output |
| Контакт 5 | AGND — Analog ground |
| Контакт 6 | REFTS — Reference top decoupling |
| Контакт 7 | REFTB — Reference bottom decoupling |
| Контакт 8 | AGND — Analog ground |
| Контакт 9 | CLKP — Sampling clock input positive |
| Контакт 10 | CLKN — Sampling clock input negative |
| Контакт 11 | MODE — LVDS/CMOS mode select |
| Контакт 12 | DVDD — Digital 3.3V supply |
| Контакт 13 | DGND — Digital ground |
| Контакт 14 | D0 — Data output bit 0 (LSB) |
| Контакт 15 | D1 — Data output bit 1 |
| Контакт 16 | D2 — Data output bit 2 |
| Контакт 17 | D3 — Data output bit 3 |
| Контакт 18 | D4 — Data output bit 4 |
| Контакт 19 | D5 — Data output bit 5 |
| Контакт 20 | D6 — Data output bit 6 |
| Контакт 21 | D7 — Data output bit 7 |
| Контакт 22 | D8 — Data output bit 8 |
| Контакт 23 | D9 — Data output bit 9 |
| Контакт 24 | D10 — Data output bit 10 |
| Контакт 25 | D11 — Data output bit 11 (MSB) |
| Контакт 26 | DRVDD — Digital output driver supply |
| Контакт 27 | DRGND — Digital output driver ground |
| Контакт 28 | CLKOUTP — DDR clock output positive (LVDS) |
| Контакт 29 | CLKOUTN — DDR clock output negative (LVDS) |
| Контакт 30 | RESET — Reset / standby control |
| Контакт 31 | PDN — Power-down control |
| Контакт 32 | EPAD — Exposed thermal pad - connect to AGND |
Типичное применение
ADS6122IRHBR подходит для 6 применениеs: Wireless Baseband IF Sampling, Medical Ultrasound Beamforming Front End, Handheld Oscilloscope and DSO Channels, Industrial Test and Measurement, Software Defined Radio Front End, Radar Signal Processing.
Wireless Baseband IF Sampling
The ADS6122IRHBR is well-suited for digitizing IF signals in wireless baseband receivers where input bandwidth stays below 30 MHz. Its 65 MSPS sample rate comfortably exceeds the Nyquist requirement for narrow-band IFs in LTE, GSM, and WCDMA receivers, while the selectable DDR LVDS output simplifies interface to high-speed FPGAs. Placed downstream of an analog AGC stage and a SAW filter, the converter delivers clean 12-bit samples with low spurious content. Compared to higher-speed family members (ADS6124, ADS6125), the ADS6122IRHBR draws less power, an advantage for densely populated multi-channel receiver cards. Engineers typically pair it with a low-jitter clock such as CDCE72010 and a differential driver like THS4520 for the analog front end.
Рекомендуется
Medical Ultrasound Beamforming Front End
In ultrasound imaging systems, the ADS6122IRHBR can be used for channel digitization in lower-frequency probes where sample rates above 80 MSPS are not required. Its 12-bit resolution and low-noise pipeline architecture provide sufficient dynamic range for echo signal processing, while the differential analog input accepts the output of typical LNA + VGA stages. The 3.3 V analog supply simplifies integration into portable cart-based ultrasound systems that already use 3.3 V rails. The selectable CMOS output mode enables direct connection to mid-range FPGAs without an LVDS deserializer, reducing BOM cost. Designers value the pin-compatible family upgrade path to ADS6125IRHBR (125 MSPS) for higher-frequency probes.
Рекомендуется
Handheld Oscilloscope and DSO Channels
The ADS6122IRHBR fits as a digitizer in mid-bandwidth handheld digital storage oscilloscopes targeting the 30-50 MHz input range. At 65 MSPS it meets the Nyquist criterion for signals up to approximately 30 MHz, which covers the bulk of general-purpose measurement tasks. The VQFN-32 5x5 mm package keeps the ADC footprint compact - critical for portable instruments where PCB real estate is at a premium. Selectable DDR LVDS mode allows fast data transfer to the host FPGA or ASIC with minimal pin count. Pairing with TI INAxxx current shunts or THS4631 front-end amplifiers enables simultaneous voltage and current probing channels in compact benchtop form factors.
Рекомендуется
Industrial Test and Measurement
Industrial data acquisition systems, vibration analyzers, and partial-discharge detectors benefit from the ADS6122IRHBR's 65 MSPS sample rate and 12-bit resolution. The pipelined architecture provides deterministic latency, simplifying synchronized sampling across multiple channels when used with a shared clock tree. The -40 C to +85 C industrial temperature range supports deployment in factory-floor and outdoor enclosures. The internal reference and high-impedance analog inputs reduce external component count, which improves MTBF in long-lifecycle industrial equipment. The selectable LVDS output helps route data over long backplane traces in modular instrumentation racks.
Рекомендуется
Software Defined Radio Front End
In narrow-band software-defined radio receivers for amateur radio, public safety, or industrial telemetry, the ADS6122IRHBR digitizes IF signals with sufficient headroom for digital demodulation in the FPGA. The DDR LVDS output mode reduces board trace count when routing 12-bit data plus clock to the host FPGA - a key consideration in compact SDR enclosures. The 12-bit resolution is adequate for many narrow-band modulation schemes (FM, GMSK, narrow-band QPSK). The pin-compatible ADS6125IRHBR (125 MSPS) provides a graceful upgrade path for wideband SDR applications such as spectrum capture. Designers typically add a SAW filter and an LNA before the ADC to maximize dynamic range.
Рекомендуется
Radar Signal Processing
Short-range radar modules for automotive parking assistance, industrial level sensing, and security motion detection can use the ADS6122IRHBR as the IF digitizer in homodyne or low-IF receiver architectures. The 65 MSPS sample rate supports carrier frequencies up to approximately 30 MHz, which covers many short-range radar bands. The selectable CMOS output enables direct connection to low-cost microcontrollers or DSPs, while the LVDS mode supports higher-performance FPGA processing. The 32-pin VQFN package provides good thermal dissipation in space-constrained radar modules, and the industrial temperature range supports outdoor mounting. Pair with a low-phase-noise oscillator and an LNA for best sensitivity.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для ADS6122IRHBR — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | ADS6123IRHBR | ADS6124IRHBR | ADS6125IRHBR | ADS6122IRHBT | ADS6122IRHB25 |
|---|---|---|---|---|---|---|
| Package | VQFN-32 (RHB) 5x5 mm | VQFN-32 (RHB) - same | VQFN-32 (RHB) - same | VQFN-32 (RHB) - same | VQFN-32 (RHB) - same | VQFN-32 (RHB) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Sample Rate | 65 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS | 65 MSPS |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Ключевые отличия
- Lowest-power member of the ADS612x pin-compatible family (против ADS6125IRHBR (125 MSPS))
- Pin-compatible upgrade path to higher sample rates (против ADS6124IRHBR (105 MSPS))
- Selectable CMOS or DDR LVDS output in a single part (против ADS6122IRHBT (reel variant))
Заметки по проектированию
The ADS6122IRHBR requires separate analog and digital 3.3 V rails. Use a low-noise LDO such as TPS7A4701 to generate the AVDD rail, and decouple each AVDD pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a 10 uF bulk capacitor. Tie the exposed thermal pad (EPAD, pin 32) to a clean analog ground pour to minimize thermal resistance. Power-supply noise directly degrades SNR, so avoid routing digital switching currents under the analog supply traces.
Route differential analog inputs INP/INN as a 100-ohm differential microstrip with matched length (within 0.5 mm) to preserve common-mode rejection. Keep the LVDS data outputs and clock traces on a different layer, with a continuous ground plane between analog and digital sections. Place anti-aliasing RC networks (typically 25 ohms + 10 pF) within 5 mm of the INP/INN pins. The MODE pin should be tied directly to AVDD or AGND with no external pull-up resistor to avoid mode contention during reset.
Do not exceed 3.6 V on any supply pin - the ADS6122IRHBR is not 5 V tolerant. Sampling clock jitter directly degrades SNR; use a low-jitter clock source such as CDCE72010 with jitter below 1 ps RMS. When operating in DDR LVDS mode, ensure the receiver FPGA supports DDR LVDS at the chosen data rate. The RESET and PDN pins must be sequenced correctly during power-up to avoid latch-up. Verify pin 1 orientation by the RHB package orientation marker before soldering reflow.
Estimated: at 65 MSPS, the Nyquist bandwidth for the analog front end is 32.5 MHz. Select a differential driver (e.g. THS4520) with at least 3x the input bandwidth to preserve settling behavior. Terminate the LVDS outputs with 100 ohms differential at the receiver. The CLKOUTP/CLKOUTN DDR clock pair must be length-matched to the data bit pairs within 1 mm to minimize setup/hold violations in the FPGA capture register.
Информация о соответствии
RoHS compliance and lead-free status confirmed per distributor listings. AEC-Q100 qualification is not applicable - this is an industrial-grade ADC. REACH, halogen-free, and conflict-mineral declarations are not stated in the verified web data.
